Hiroyuki Ochi

Publication Activity (10 Years)

Years Active: 1991-2023
Publications (10 Years): 16

Top Topics

Error Tolerance

Reconfigurable Architecture

Signal Processing

Programmable Logic

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. IEICE Trans. Electron. 106 (10) (2023)
Xuanqi Li, Takashi Imagawa, Hiroyuki Ochi
Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction. ASICON (2023)
Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi
A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor. IPSJ Trans. Syst. LSI Des. Methodol. 16 (2023)
Renya Makimoto, Takashi Imagawa, Hiroyuki Ochi
Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments. SOCC (2023)
Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. COOL CHIPS (2022)
Yuki Abe, Kazutoshi Kobayashi, Hiroyuki Ochi
Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations. MWSCAS (2022)
Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. DATE (2021)
Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi
Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. COOL CHIPS (2021)
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC (2020)
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10 (4) (2018)
Toshiki Higashi, Hiroyuki Ochi
Area-Efficient LUT-Like Programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Takashi Imagawa, Koki Honda, Hiroyuki Ochi
Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. SoCC (2017)
Ryosuke Koike, Takashi Imagawa, Roberto Yusi Omaki, Hiroyuki Ochi
Selectable grained reconfigurable architecture (SGRA) and its design automation. SoCC (2017)
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL (2016)
Takashi Kishimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Hiroyuki Ochi
Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. IEICE Trans. Electron. (7) (2015)
Toshiki Higashi, Hiroyuki Ochi
Area-efficient LUT-like programmable logic using atom switch and its mapping algorithm. ISCIT (2015)
Tomoya Kimura, Hiroyuki Ochi
A -0.5V-input voltage booster circuit for on-chip solar cells in 0.18µm CMOS technology. ISCIT (2015)
Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC (2015)
Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. ISQED (2014)
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. IEICE Trans. Electron. (4) (2013)
Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis. ACM Great Lakes Symposium on VLSI (2013)
Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE (2013)
Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. ISQED (2013)
Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
Realization of frequency-domain circuit analysis through random walk. ASP-DAC (2013)
Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. DATE (2013)
Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
Multi-trap RTN parameter extraction based on Bayesian inference. ISQED (2013)
Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element. IEICE Trans. Electron. (4) (2013)
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig (2013)
Hiroyuki Ochi, Toshihiko Ota, Ataru Yamaoka, Hiromasa Watanabe, Yohei Kondo, Nobuyuki Tokuda, Hiroyuki Taguchi, Taketoshi Matsumoto, Tomoki Akai, Hikaru Kobayashi, Shigeki Imai
Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation. SoCC (2013)
Takashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. ISQED (2012)
Hiroshi Tsutsui, Koichi Hattori, Hiroyuki Ochi, Yukihiro Nakamura
A high-throughput pipelined parallel architecture for JPEG XR encoding. ACM Trans. Embed. Comput. Syst. 11 (4) (2012)
Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. ISQED (2011)
Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
Acceleration of random-walk-based linear circuit analysis using importance sampling. ACM Great Lakes Symposium on VLSI (2011)
Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato
A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. SoCC (2011)
Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC (2010)
Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. ICCAD (2010)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Scan based process parameter estimation through path-delay inequalities. ISCAS (2010)
Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Path clustering for adaptive test. VTS (2010)
Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura
Dynamic rate control for media streaming in high-speed mobile networks. WCNC (2009)
Ryoji Kadota, Hiroki Sugano, Masayuki Hiromoto, Hiroyuki Ochi, Ryusuke Miyamoto, Yukihiro Nakamura
Hardware Architecture for HOG Feature Extraction. IIH-MSP (2009)
Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
Efficient Memory Organization Framework for JPEG2000 Entropy Codec. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2009)
Hiroki Sugano, Hiroyuki Ochi, Yukihiro Nakamura, Ryusuke Miyamoto
Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2009)
Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye
Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL (2009)
Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
A high-throughput pipelined architecture for JPEG XR encoding. ESTIMedia (2009)
Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
Hot-Swapping architecture extension for mitigation of permanent functional unit faults. FPL (2009)
Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
An architecture of photo core transform in HD photo coding system for embedded systems of various bandwidths. APCCAS (2008)
Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2007)
Norihiro Ishikawa, Hiroshi Tsutsui, Jaehoon Yu, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, Takaaki Komura, Yoshitaka Uchida
Implementation of AV Streaming System Using Peer-to-Peer Communication. CCNC (2007)
Hiromitsu Sumino, Norihiro Ishikawa, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura, Yoshitaka Uchida
Home Appliance Control from Mobile Phones. CCNC (2007)
Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura
Network Processor for High-Speed Network and Quick Programming. J. Circuits Syst. Comput. 16 (1) (2007)
Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Ryusuke Miyamoto, Hiroki Sugano, Hiroaki Saito, Hiroshi Tsutsui, Hiroyuki Ochi, Ken'ichi Hatanaka, Yukihiro Nakamura
Pedestrian Recognition in Far-Infrared Images by Combining Boosting-Based Detection and Skeleton-Based Stochastic Tracking. PSIVT (2006)
Hiroyuki Ochi, Shigeaki Tagashira, Satoshi Fujita
A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups. IEICE Trans. Inf. Syst. (5) (2006)
Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
Efficient memory architecture for JPEG2000 entropy codec. ISCAS (2006)
Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. FPGA (2006)
Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells. FPL (2006)
Tomonori Izumi, Shin'ichi Kouyama, Hiroyuki Ochi, Yukihiro Nakamura
An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Hiroyuki Ochi, Shigeaki Tagashira, Satoshi Fujita
A Localization Scheme for Sensor Networks based onWireless Communication with Anchor Groups. ICPADS (1) (2005)
Hiroyuki Ochi, Tatsuya Suzuki, Sayaka Matsunaga, Yoichi Kawano, Takao Tsuda
Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Takahiro Kakimoto, Hiroyuki Ochi, Takao Tsuda
Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Yeol Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. ASP-DAC (2000)
Hiroyuki Ochi, Koichi Yasuoka, Shuzo Yajima
Breadth-first manipulation of very large binary-decision diagrams. ICCAD (1993)
Hiromi Hiraishi, Kiyoharu Hamaguchi, Hiroyuki Ochi, Shuzo Yajima
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. CAV (1991)
Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. DAC (1991)