A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL.
Hirofumi SakamotoKen'ichiro UdaBu-Yeol LeeHiroyuki OchiKazuo TakiTakao TsudaPublished in: ASP-DAC (2000)
Keyphrases
- low power
- spl times
- logical operations
- cmos technology
- logic circuits
- high speed
- power consumption
- low cost
- delay insensitive
- multi valued
- random access memory
- low voltage
- single chip
- high power
- digital signal processing
- power dissipation
- wireless transmission
- vlsi architecture
- mixed signal
- low power consumption
- floating point
- non binary
- power reduction
- video camera
- hardware implementation
- nm technology