Akira Nagoya

Publication Activity (10 Years)

Years Active: 1990-2022
Publications (10 Years): 2

Top Topics

Planning Systems

Convolutional Neural Network

Parallel Implementations

Top Venues

CANDAR Workshops

Publications

Akihiko Ushiroyama, Minoru Watanabe, Nobuya Watanabe, Akira Nagoya
Convolutional neural network implementations using Vitis AI. CCWC (2022)
Masao Yamamoto, Kohta Nakashima, Toshihiro Yamauchi, Akira Nagoya, Hideo Taniguchi
Acceleration of Analysis Processing on Decentralized Performance Profiling System Using Virtual Machines. CANDAR Workshops (2018)
Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura
Network Processor for High-Speed Network and Quick Programming. J. Circuits Syst. Comput. 16 (1) (2007)
Hideyuki Ito, Ryusuke Konishi, Hiroshi Nakada, Hideyuki Tsuboi, Yuichi Okuyama, Akira Nagoya
Dynamically Reconfigurable Logic LSI: PCA-2. IEICE Trans. Inf. Syst. (8) (2004)
Yoshiki Nakane, Kouichi Nagami, Tsunemichi Shiozawa, Akira Nagoya
Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture. FPT (2003)
Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya
Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. Asia-Pacific Computer Systems Architecture Conference (2003)
Minoru Inamori, Hiroshi Nakada, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri
A Method of Mapping Finite State Machine into PCA Plastic Parts. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2002)
Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. ASYNC (2001)
Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada, Akira Nagoya
Solving satisfiability problems using reconfigurable computing. IEEE Trans. Very Large Scale Integr. Syst. 9 (1) (2001)
Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig
Self-reorganising systems on VLSI circuits. ISCAS (4) (2001)
Norbert Imlig, Tsunemichi Shiozawa, Kouichi Nagami, Yoshiki Nakane, Ryusuke Konishi, Hideyuki Ito, Akira Nagoya
Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture. IPDPS (2001)
Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. FPL (2000)
Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology. FPL (2000)
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
SPFD: A new method to express functional flexibility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (8) (2000)
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. ASP-DAC (2000)
Takayuki Suyama, Makoto Yokoo, Akira Nagoya
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic. IPPS/SPDP Workshops (1999)
Akihiro Matsuura, Hidehisa Nagano, Akira Nagoya
A Method for Implementing Fractal Image Compression on Reconfigurable Architecture. FPGA (1999)
Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya
An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture. IPPS/SPDP Workshops (1999)
Akihiro Matsuura, Akira Nagoya
Summation Algorithms on Constrained Reconfigurable Meshes. ISPAN (1999)
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
An Integrated Approach for Synthesizing LUT Networks. Great Lakes Symposium on VLSI (1999)
Takayuki Suyama, Makoto Yokoo, Akira Nagoya
Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation. CP (1999)
Hidehisa Nagano, Takayuki Suyama, Akira Nagoya
Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach. ASP-DAC (1999)
Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. DATE (1998)
Hidehisa Nagano, Takayuki Suyama, Akira Nagoya
Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract). FPGA (1998)
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
New Methods to Find Optimal Non-Disjoint Bi-Decompositions. ASP-DAC (1998)
Kaihiro Matsuura, Akira Nagoya
Formulation of the Addition-Shift-Sequence Problem and Its Complexity. ISAAC (1997)
Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. Great Lakes Symposium on VLSI (1997)
Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. CODES (1997)
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
A new method to express functional permissibilities for LUT based FPGAs and its applications. ICCAD (1996)
Takayuki Suyama, Hiroshi Sawada, Akira Nagoya
LUT-based FPGA Technology Mapping using Permissible Functions. VLSI Design (1996)
Hiroshi Sawada, Takayuki Suyama, Akira Nagoya
Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. ICCAD (1995)
Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura
Multi-Level Optimization for Large Scale ASICS. ICCAD (1990)