Kazuya Masu

ORCID

Publication Activity (10 Years)

Years Active: 1994-2021
Publications (10 Years): 18

Top Venues

ASP-DAC

IEEE SENSORS

IEICE Trans. Electron.

A-SSCC

Publications

Kohei Shibata, Akihiro Uchiyama, Akira Onishi, Shinichi Iida, Toshifumi Konishi, Noboru Ishihara, Katsuyuki Machida, Kazuya Masu, Hiroyuki Ito
A Simplified Analytical Damping Constant Model for Perforated Proof Mass Structure of MEMS Capacitive Accelerometer by Multi-Layer Metal Technology. IEEE SENSORS (2021)
Ludovico Minati, Korkut Kaan Tokgoz, Mattia Frasca, Yasuharu Koike, Jacopo Iannacci, Natsue Yoshimura, Kazuya Masu, Hiroyuki Ito
Distributed Sensing Via Inductively Coupled Single-Transistor Chaotic Oscillators: A New Approach and Its Experimental Proof-of-Concept. IEEE Access 8 (2020)
Tatsuya Koga, Katsuyuki Machida, Yoshihiro Miyake, Kazuya Masu, Takashi Ichikawa, Naoto Tanaka, Taiki Ogata, Hiroki Ora, Daisuke Yamane, Noboru Ishihara, Hiroyuki Ito, Masato Sone
High-Sensitivity Inertial Sensor Module to Measure Hidden Micro Muscular Sounds. BioCAS (2019)
Kyotaro Nitta, Masato Sone, Haochun Tang, Chun-Yi Chen, Tso-Fu Mark Chang, Daisuke Yamane, Shinichi Iida, Katsuyuki Machida, Hiroyuki Ito, Kazuya Masu
Fabrication of Au-Cu Alloy/Ti Layered Micro-Cantilevers and the Long-Term Structure Stability. IEEE SENSORS (2019)
Ludovico Minati, Mattia Frasca, Natsue Yoshimura, Leonardo Ricci, Pawel Oswiecimka, Yasuharu Koike, Kazuya Masu, Hiroyuki Ito
Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades. IEEE Access 7 (2019)
Motohiro Takayasu, Shiro Dosho, Hiroyuki Ito, Daisuke Yamane, Toshifumi Konishi, Katsuyuki Machida, Noboru Ishihara, Kazuya Masu
A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers. IEICE Electron. Express 15 (2) (2018)
Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique. IEEE J. Solid State Circuits 52 (4) (2017)
Hideaki Nakajima, Tso-Fu Mark Chang, Chun-Yi Chen, Toshifumi Konishi, Katsuyuki Machida, Hiroshi Toshiyoshi, Daisuke Yamane, Kazuya Masu, Masato Sone
A study on young's modulus of electroplated gold cantilevers for MEMS devices. NEMS (2017)
Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. ASP-DAC (2017)
Yuta Oshima, Iwao Mizumoto, Hiroshi Oguma, Noboru Ishihara, Kazuya Masu
Estimation of energy self-sufficiency rate by EMS simulation using SPICE. ICTC (2017)
Yuta Oshima, Hiroshi Oguma, Noboru Ishihara, Kazuya Masu
Simulation and evaluation of PV power generation for energy management system using SPICE. ICTC (2016)
Toshifumi Konishi, Teruaki Safu, Katsuyuki Machida, Daisuke Yamane, Masato Sone, Kazuya Masu, Hiroshi Toshiyoshi
A damping constant model for proof-mass structure design of MEMS inertial sensor by multi-layer metal technology. IEEE SENSORS (2016)
Kazuya Masu, Daisuke Yamane, Katsuyuki Machida, Masato Sone, Yoshihiro Miyake
Development of high sensitivity CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson's disease. ESSCIRC (2016)
Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. 32 (5) (2016)
Daisuke Yamane, Toshifumi Konishi, Teruaki Safu, Hiroshi Toshiyoshi, Masato Sone, Kazuya Masu, Katsuyuki Machida
A design of spring constant arranged for MEMS accelerometer by multi-layer metal technology. NEMS (2016)
Kohei Ohba, Yoshihiro Yoneda, Koji Kurihara, Takashi Suganuma, Hiroyuki Ito, Noboru Ishihara, Kunihiko Gotoh, Koichiro Yamashita, Kazuya Masu
Environmental Data Recovery using Polynomial Regression for Large-scale Wireless Sensor Networks. SENSORNETS (2016)
Daisuke Yamane, Toshifumi Konishi, Teruaki Safu, Hiroshi Toshiyoshi, Masato Sone, Kazuya Masu, Katsuyuki Machida
Evaluation and modeling of adhesion layer in shock-protection structure for MEMS accelerometer. Microelectron. Reliab. 66 (2016)
Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. VLSI Circuits (2016)
Atsushi Shirane, Yiming Fang, Haowei Tan, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter. IEEE J. Solid State Circuits 50 (12) (2015)
Atsushi Shirane, Haowei Tan, Yiming Fang, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
13.8 A 5.8GHz RF-powered transceiver with a 113μW 32-QAM transmitter employing the IF-based quadrature backscattering technique. ISSCC (2015)
Sho Ikeda, Sang-yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network. ASP-DAC (2015)
Yosuke Ishikawa, Sang-yeop Lee, Shin Yonezawa, Sho Ikeda, Yiming Fang, Taisuke Hamada, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna. ISCAS (2015)
Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor. ASP-DAC (2014)
Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS. IEICE Trans. Electron. (6) (2014)
Sho Ikeda, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET. A-SSCC (2014)
Shiho Hagiwara, Takanori Date, Kazuya Masu, Takashi Sato
Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis. IEICE Trans. Electron. (4) (2014)
Yusuke Shiino, Hiroyuki Ito, Taku Fujiwara, Noboru Ishihara, Hisashi Yamanouchi, Hiroki Tanabe, Satoshi Nomura, Toshifumi Konishi, Katsuyuki Machida, Kazuya Masu
An ultra low power pH-monitoring IC with a duty-cycling wireless FM-transmitter. ISCAS (2014)
Taisuke Hamada, Hao Jiang, Yiming Fang, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A 0.5-V 2.5-GHz high-gain low-power regenerative amplifier based on Colpitts oscillator topology in 65-nm CMOS. APCCAS (2014)
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato
A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (7) (2014)
Koh Yamanaga, Shiho Hagiwara, Ryo Takahashi, Kazuya Masu, Takashi Sato
State-Dependence of On-Chip Power Distribution Network Capacitance. IEICE Trans. Electron. (1) (2014)
Hiroyuki Ito, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, Noboru Ishihara, Kazuya Masu, Shoichi Masui, Youichi Momiyama
An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI. A-SSCC (2014)
Hiroshi Toshiyoshi, Toshifumi Konishi, Katsuyuki Machida, Kazuya Masu
A mixed-design technique for integrated MEMS using a circuit simulator with HDL. MIXDES (2013)
Kazuya Masu, Noboru Ishihara, Toshifumi Konishi, Katsuyuki Machida, Hiroshi Toshiyoshi
Challenges in integration of diverse functionalities on CMOS. ASP-DAC (2013)
Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A process-scalable RF transmitter using 90nm and 65nm Si CMOS. VLSI-DAT (2013)
Hamid Kiumarsi, Hiroyuki Ito, Kenichi Okada, Yusuke Uemichi, Yasuto Chiba, Noboru Ishihara, Kazuya Masu
A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate. IEICE Electron. Express 10 (2) (2013)
Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
Optimal design method for chip-area-efficient CMOS low-dropout regulator. APCCAS (2012)
Sang-yeop Lee, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, Kazuya Masu
Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique. IEICE Electron. Express 9 (21) (2012)
Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS. IEICE Trans. Electron. (10) (2012)
Kazuo Nakano, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
RF signal generator using time domain harmonic suppression technique in 90nm CMOS. IEICE Electron. Express 9 (4) (2012)
Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. ISOCC (2011)
Noboru Ishihara, Shuhei Amakawa, Kazuya Masu
RF CMOS Integrated Circuit: History, Current Status and Future Prospects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2011)
Yusaku Ito, Kenichi Okada, Kazuya Masu
A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers. J. Electr. Comput. Eng. 2011 (2011)
Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOS. ISOCC (2011)
Koh Yamanaga, Shuhei Amakawa, Kazuya Masu, Takashi Sato
A Universal Equivalent Circuit Model for Ceramic Capacitors. IEICE Trans. Electron. (3) (2010)
Takumi Uezono, Kazuya Masu, Takashi Sato
A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation. IEICE Trans. Electron. (3) (2010)
Takashi Sato, Takumi Uezono, Noriaki Nakayama, Kazuya Masu
Decomposition of drain-current variation into gain-factor and threshold voltage variations. ISCAS (2010)
Takanori Date, Shiho Hagiwara, Kazuya Masu, Takashi Sato
Robust importance sampling for efficient SRAM yield analysis. ISQED (2010)
Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato
Linear time calculation of state-dependent power distribution network capacitance. ISQED (2010)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Scan based process parameter estimation through path-delay inequalities. ISCAS (2010)
Mousa M. Othman, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
Wide-band, high linear low noise amplifier design in 0.18um CMOS technology. IEICE Electron. Express 7 (11) (2010)
Toshiyuki Umeda, Kazuya Masu
A study for the efficiency of transmission energy for different high-frequency communication circuits. IEICE Electron. Express 7 (8) (2010)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Path clustering for adaptive test. VTS (2010)
Koh Yamanaga, Kazuya Masu, Takashi Sato
Application of generalized scattering matrix for prediction of power supply noise. SLIP (2010)
Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato
Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Shiho Hagiwara, Takashi Sato, Kazuya Masu
Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Tomoaki Maekawa, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique. ECCTD (2009)
Takumi Uezono, Takashi Sato, Kazuya Masu
One-Shot Voltage-Measurement Circuit Utilizing Process Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu
Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors. IEEE J. Solid State Circuits 44 (11) (2009)
Takeshi Ito, Kenichi Okada, Kazuya Masu
Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2009)
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium (2009)
Yuka Kobayashi, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS. ESSCIRC (2009)
Hirotaka Sugawara, Kenichi Okada, Kazuya Masu
Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2009)
Kazuya Masu, Noboru Ishihara, Noriaki Nakayama, Takashi Sato, Shuhei Amakawa
Physical design challenges to nano-CMOS circuits. IEICE Electron. Express 6 (11) (2009)
Koh Yamanaga, Takashi Sato, Kazuya Masu
2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Trans. Electron. (7) (2008)
Kazuya Masu, Kenichi Okada
Reconfigurable RF CMOS Circuit for Cognitive Radio. IEICE Trans. Commun. (1) (2008)
Tackya Yammouch, Kenichi Okada, Kazuya Masu
Physical Modeling of MEMS Variable Inductor. IEEE Trans. Circuits Syst. II Express Briefs (5) (2008)
Hiroyuki Ito, Hasnain Lakdawala, Ashoke Ravi, Stefano Pellerano, Rick Ruby, Krishnamurthy Soumyanath, Kazuya Masu
A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution. ESSCIRC (2008)
Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
Small-area CMOS RF distributed mixer using multi-port inductors. ASP-DAC (2008)
Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. ASP-DAC (2008)
Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu
Determination of optimal polynomial regression function to decompose on-die systematic and random variations. ASP-DAC (2008)
Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu
A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications. IEEE J. Solid State Circuits 43 (4) (2008)
Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. DAC (2008)
Tomoaki Maekawa, Hiroyuki Ito, Kazuya Masu
An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx. ESSCIRC (2008)
Kazuma Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu
A Wideband CMOS LC-VCO Using Variable Inductor. ASP-DAC (2007)
Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED (2007)
Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu
Improvement of power distribution network using correlation-based regression analysis. ACM Great Lakes Symposium on VLSI (2007)
Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu
Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. ASP-DAC (2007)
Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu
A Multi-Drop Transmission-Line Interconnect in Si LSI. ASP-DAC (2007)
Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu
Adaptable wire-length distribution with tunable occupation probability. SLIP (2007)
Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu
Weakness Identification for Effective Repair of Power Distribution Network. PATMOS (2007)
Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, Ryozo Yamauchi, Kazuya Masu
Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology. IEICE Trans. Electron. (3) (2007)
D. Kawazoe, Hirotaka Sugawara, Tatsuya Ito, Kenichi Okada, Kazuya Masu
Reconfigurable CMOS low noise amplifier for self compensation. ISCAS (2006)
Kenichi Okada, Takumi Uezono, Kazuya Masu
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. PATMOS (2006)
Takumi Uezono, Kenichi Okada, Kazuya Masu
Via Distribution Model for Yield Estimation. ISQED (2006)
Kazuya Masu, Kenichi Okada, Hiroyuki Ito
RF Passive Components Using Metal Line on Si CMOS. IEICE Trans. Electron. (6) (2006)
Takumi Uezono, Kenichi Okada, Kazuya Masu
Statistical Modeling of a Via Distribution for Yield Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu
Wire Length Distribution Model Considering Core Utilization for System on Chip. ISVLSI (2005)
Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu
Evaluation of on-chip transmission line interconnect using wire length distribution. ASP-DAC (2005)
Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu
Wire Length Distribution Model for System LSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu
A dynamic reconfigurable RF circuit architecture. ASP-DAC (2005)
Hidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu
Evaluation of X Architecture Using Interconnect Length Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2005)
Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu
Prediction of delay time for future LSI using on-chip transmission line interconnects. SLIP (2005)
Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu
ULSI Interconnect Length Distribution Model Considering Core Utilization. DATE (2004)
Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design. IEICE Electron. Express 1 (7) (2004)
Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
Differential transmission line interconnect for high speed and low power global wiring. CICC (2004)

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Publication Activity (10 Years)

Top Topics

Top Venues

Kazuya Masu