Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits.
Shiho HagiwaraTakashi SatoKazuya MasuPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2009)
Keyphrases
- power dissipation
- analog vlsi
- delay insensitive
- high speed
- circuit design
- power consumption
- low cost
- vlsi circuits
- cmos technology
- low power
- accurate estimation
- estimation accuracy
- parameter estimation
- low voltage
- multicast tree
- chip design
- random access memory
- density estimation
- estimation process
- path length
- estimation algorithm
- analog circuits
- asynchronous circuits
- estimation error
- neural network
- destination node