A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS.
Sho IkedaSang-yeop LeeTatsuya KamimuraHiroyuki ItoNoboru IshiharaKazuya MasuPublished in: IEICE Trans. Electron. (2014)
Keyphrases
- low voltage
- cmos technology
- low power
- power consumption
- ultra low power
- power line
- power management
- leakage current
- random access memory
- design considerations
- high speed
- low cost
- power supply
- mixed signal
- power dissipation
- data center
- energy efficiency
- parallel processing
- energy consumption
- nm technology
- silicon on insulator