A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOS.
Atsushi ShiraneHiroyuki ItoNoboru IshiharaKazuya MasuPublished in: ISOCC (2011)
Keyphrases
- circuit design
- high speed
- analog vlsi
- low voltage
- delay insensitive
- vlsi circuits
- cmos technology
- charge coupled devices
- power consumption
- leakage current
- digital circuits
- analog circuits
- variance reduction
- power dissipation
- multiple input
- low power
- logic circuits
- power supply
- electricity markets
- multiple output
- data acquisition