Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.

Kenichi Okada Takumi Uezono Kazuya Masu

Published in: PATMOS (2006)

Keyphrases

nm technology
power consumption
power reduction
transmission line
power dissipation
low power
power saving
high speed
power system
differential equations
energy efficiency
digital signal processing
low cost
energy saving
artificial intelligence
operating conditions
finite state machines
data center