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A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor.

Sho IkedaTatsuya KamimuraSang-yeop LeeHiroyuki ItoNoboru IshiharaKazuya Masu
Published in: ASP-DAC (2014)
Keyphrases
  • low voltage
  • power line
  • design considerations
  • power management
  • high speed
  • multi view
  • power consumption
  • cmos technology
  • image processing