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A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor.
Sho Ikeda
Tatsuya Kamimura
Sang-yeop Lee
Hiroyuki Ito
Noboru Ishihara
Kazuya Masu
Published in:
ASP-DAC (2014)
Keyphrases
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low voltage
power line
design considerations
power management
high speed
multi view
power consumption
cmos technology
image processing