Shigetaka Kumashiro

Publication Activity (10 Years)

Years Active: 1993-2023
Publications (10 Years): 2

Top Topics

Simulation Model

Top Venues

IEICE Trans. Electron.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Kazutoshi Kobayashi, Tomoharu Kishita, Hiroki Nakano, Jun Furuta, Mitsuhiko Igarashi, Shigetaka Kumashiro, Michitarou Yabuuchi, Hironori Sakamoto
Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators. IRPS (2023)
Shigetaka Kumashiro, Tatsuya Kamei, Akira Hiroki, Kazutoshi Kobayashi
An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Shigetaka Kumashiro
A predictable compact model for non-monotonous Vth-Pelgrom plot of long channel halo-implanted transistors. ISQED (2013)
Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. IEICE Trans. Electron. (6) (2013)
Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
and Signal/Substrate Response of Differential Pair Transistors. IEICE Trans. Electron. (1) (2012)
Hironori Sakamoto, Shigetaka Kumashiro, Shigeo Sato, Naoki Wakita, Tohru Mogami
principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS. ISQED (2012)
Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Trans. Electron. (4) (2011)
Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Trans. Electron. (6) (2011)
Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED (2011)
Kenta Yamada, Toshiyuki Syo, Hisao Yoshimura, Masaru Ito, Tatsuya Kunikiyo, Toshiki Kanamoto, Shigetaka Kumashiro
Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns. IEICE Trans. Electron. (8) (2010)
Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Trans. Electron. (7) (2008)
Tatsuya Ezaki, Dondee Navarro, Youichi Takeda, Norio Sadachika, Gaku Suzuki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. Math. Comput. Simul. 79 (4) (2008)
Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. IEICE Trans. Electron. (5) (2005)
Shizunori Matsumoto, Hiroaki Ueno, Satoshi Hosokawa, Toshihiko Kitamura, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. IEICE Trans. Electron. (2) (2005)
Youichi Takeda, Dondee Navarro, Shingo Chiba, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto
MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime. CICC (2005)
Kazuya Hisamitsu, Hiroaki Ueno, Masayasu Tanaka, Daisuke Kitamaru, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. ASP-DAC (2003)
Mitiko Miura-Mattausch, Hiroaki Ueno, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
Circuit Simulation Models for Coming MOSFET Generations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2002)
D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
Correlation method of circuit-performance and technology fluctuations for improved design reliability. ASP-DAC (2001)
Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. CICC (2001)
Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (7) (1993)