Jun Furuta

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 23

Top Topics

Measurement Errors

Top Venues

IEICE Trans. Electron.

Publications

Ryuichi Nakajima, Takafumi Ito, Shotaro Sugitani, Tomoya Kii, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard
Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies. IEICE Trans. Electron. 107 (7) (2024)
Jun Furuta, Shotaro Sugitani, Ryuichi Nakajima, Kazutoshi Kobayashi
A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead. IRPS (2024)
Ryuichi Nakajima, Shotaro Sugitani, Haruto Sugisaki, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Makoto Sakai
An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/ u Carbon Beam and Particle Transport Simulations. IRPS (2024)
Shotaro Sugitani, Ryuichi Nakajima, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi
Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process. IRPS (2023)
Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi
Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements. ICICDT (2023)
Keita Yoshida, Ryuichi Nakajima, Shotaro Sugitani, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi
SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation. ICICDT (2023)
Kazutoshi Kobayashi, Tomoharu Kishita, Hiroki Nakano, Jun Furuta, Mitsuhiko Igarashi, Shigetaka Kumashiro, Michitarou Yabuuchi, Hironori Sakamoto
Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators. IRPS (2023)
Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard
Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation. IOLTS (2023)
Ryuichi Nakajima, Kazuya Ioki, Jun Furuta, Kazutoshi Kobayashi
Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process. IOLTS (2022)
Junichiro Nagao, Urmimala Chatterjee, Xiangdong Li, Jun Furuta, Stefaan Decoutere, Kazutoshi Kobayashi
An E-mode p-GaN HEMT monolithically-integrated three-level gate driver operating with a single voltage supply. IEICE Electron. Express 18 (6) (2021)
Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters. IEICE Trans. Electron. (4) (2020)
Takuya Asuke, Ryo Kishida, Jun Furuta, Kazutoshi Kobayashi
Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation. ASICON (2019)
Yuki Yamashita, Steve Stoffels, Niels Posthuma, Karen Geens, Xiangdong Li, Jun Furuta, Stefaan Decoutere, Kazutoshi Kobayashi
Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process. IEICE Electron. Express 16 (22) (2019)
Jun Furuta, Yuto Tsukita, Kodai Yamada, Mitsunori Ebara, Kentaro Kojima, Kazutoshi Kobayashi
Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process. IRPS (2019)
Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer. IRPS (2019)
Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process. IOLTS (2019)
Yuto Tsukita, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi
Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process. ASICON (2019)
Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe
Characterizing SRAM and FF soft error rates with measurement and simulation. Integr. 69 (2019)
Takashi Yoshida, Kazutoshi Kobayashi, Jun Furuta
Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process. IOLTS (2019)
Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi
Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. IRPS (2018)
Haruki Maruoka, Masashi Hifumi, Jun Furuta, Kazutoshi Kobayashi
A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process. IEICE Trans. Electron. (4) (2018)
Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. ICICDT (2017)
Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi
Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets. IEICE Trans. Electron. (4) (2015)
Kuiyuan Zhang, Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect. IEICE Trans. Electron. (4) (2013)
Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. A-SSCC (2011)
Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. ASP-DAC (2011)
Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity. IEICE Trans. Electron. (3) (2010)