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Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process.

Jun FurutaYuto TsukitaKodai YamadaMitsunori EbaraKentaro KojimaKazutoshi Kobayashi
Published in: IRPS (2019)
Keyphrases
  • events occurring
  • event detection
  • low power
  • real time
  • case study
  • pattern matching
  • power dissipation