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A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process.
Haruki Maruoka
Masashi Hifumi
Jun Furuta
Kazutoshi Kobayashi
Published in:
IEICE Trans. Electron. (2018)
Keyphrases
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low power
cmos technology
power consumption
low cost
high speed
power dissipation
single chip
high power
flip flops
logic circuits
mixed signal
wireless transmission
vlsi circuits
nm technology
digital signal processing
x ray
low voltage
parallel processing
image sensor
infrared
vlsi architecture