Satoru Tanoi

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 2

Top Topics

Rolling Shutter

Cmos Image Sensor

Top Venues

IEICE Trans. Electron.

Publications

Shunichi Kubo, Yuji Gendai, Satoshi Miura, Shinsuke Hara, Satoru Tanoi, Akifumi Kasarnatsu, Takeshi Yoshida, Satoshi Tanaka, Shuhei Arnakawa, Minoru Fujishlrna
A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs. CICC (2024)
Shinsuke Hara, Ruibing Dong, Sangyeop Lee, Kyoya Takano, Naoya Toshida, Satoru Tanoi, Tatsuo Hagino, Mohamed H. Mubarak, Norihiko Sekine, Issei Watanabe, Akifumi Kasamatsu, Kunio Sakakibara, Shunichi Kubo, Satoshi Miura, Yohtaro Umeda, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima
A 76-Gbit/s 265-GHz CMOS Receiver. A-SSCC (2021)
Satoru Tanoi, Tetsuo Endoh
A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs. IEICE Trans. Electron. (5) (2014)
Sang-yeop Lee, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, Kazuya Masu
Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique. IEICE Electron. Express 9 (21) (2012)
Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS. IEICE Trans. Electron. (10) (2012)
Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. ISOCC (2011)
Akifumi Kasamatsu, Akio Tanaka, Hiroshi Kodama, Satoru Tanoi, Yasuhiro Kaizaki, Juichi Nakada, Masami Hagio, Yoshiaki Kuraishi, Keren Li, Hitoshi Utagawa, Toshiaki Matsui, Ryuji Kohno
RF-CMOS Implementation of UWB Transceivers and Its Application to Video Transmission. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2005)
Satoru Tanoi
BIST: required for embedded DRAM. ITC (1998)
Satoru Tanoi, Yasuhiro Tokunaga, Tetsuya Tanabe, Kazuhiko Takahashi, Atsuhiko Okada, Masahiro Itoh, Yoshiki Nagatomo, Yoshio Ohtsuki, Masaru Uesugi
On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM. IEEE J. Solid State Circuits 32 (11) (1997)
Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. IEEE J. Solid State Circuits 31 (4) (1996)
Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi
A 32-bank 256-Mb DRAM with cache and TAG. IEEE J. Solid State Circuits 29 (11) (1994)