A 32-bank 256-Mb DRAM with cache and TAG.
Satoru TanoiYasuhiro TanakaTetsuya TanabeAkio EtaToshio InadaRyoji HamazakiYoshio OhtsukiMasaru UesugiPublished in: IEEE J. Solid State Circuits (1994)
Keyphrases
- main memory
- memory subsystem
- dynamic random access memory
- hard disk
- data structure
- database management systems
- times faster
- memory hierarchy
- cache misses
- index structure
- ibm zenterprise
- high density
- tag recommendation
- keywords
- social annotations
- rfid tags
- memory access
- low voltage
- macroblock
- query processing
- hit rate
- social tagging
- cache management
- inter frame
- data access