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A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture.
Satoru Tanoi
Tetsuya Tanabe
Kazuhiko Takahashi
Sanpei Miyamoto
Masaru Uesugi
Published in:
IEEE J. Solid State Circuits (1996)
Keyphrases
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high speed
fpga device
management system
real time
software architecture
hardware implementation
master slave
high frequency
power consumption
nm technology
clock frequency
parallel architecture
design methodology
data flow
low cost
wireless sensor networks
website
neural network