Yukio Mitsuyama

Publication Activity (10 Years)

Years Active: 1999-2021
Publications (10 Years): 9

Top Topics

Random Number Generator

Reconfigurable Architecture

Autonomous Driving

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Ryohei Yamamoto, Yuki Izumi, Ryo Aono, Takumi Nagahara, Tomonari Tanaka, Wang Liao, Yukio Mitsuyama
Development of Autonomous Driving System based on Image Recognition using Programmable SoCs. FPT (2021)
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC (2020)
Wang Liao, Kojiro Ito, Yukio Mitsuyama, Masanori Hashimoto
Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs. IRPS (2020)
Yukio Mitsuyama, Takashi Asada, Makio Eguchi
Measurement of Variations in FPGAs under Various Load Conditions. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Tomonari Tanaka, Itsuki Ikeno, Riku Tsuruoka, Takumi Kuchiba, Wang Liao, Yukio Mitsuyama
Development of Autonomous Driving System Using Programmable SoCs. FPT (2019)
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10 (4) (2018)
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL (2016)
Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC (2015)
Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2014)
Yukio Mitsuyama, Hidetoshi Onodera
Variability and Soft-Error Resilience in Dependable VLSI Platform. ATS (2014)
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2014)
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Hiroaki Konoura, Takashi Imagawa, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2014)
Dawood Alnajiar, Hiroaki Konoura, Younghun Ko, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling. IEEE Trans. Inf. Forensics Secur. 8 (8) (2013)
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig (2013)
Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices. IEICE Electron. Express 10 (5) (2013)
Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices. IEICE Trans. Inf. Syst. (8) (2013)
Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. FPL (2012)
Dawood Alnajiar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. ReConFig (2012)
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. PATMOS (2011)
Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Stress Probability Computation for Estimating NBTI-Induced Delay Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. FPL (2011)
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 18 (7) (2010)
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC (2010)
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. ISQED (2010)
Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. ISQED (2010)
Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. WISA (2010)
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC (2009)
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC (2009)
Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye
Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL (2009)
Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. ISLPED (2009)
Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Trans. Electron. (2) (2009)
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED (2008)
Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa
Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI (2008)
Yukio Mitsuyama, Motoki Kimura, Takao Onoye, Isao Shirakawa
Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
Burst mode: a new acceleration mode for 128-bit block ciphers. CICC (2002)
Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
VLSI architecture of dynamically reconfigurable hardware-based cipher. ISCAS (4) (2001)
Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
A dynamically reconfigurable hardware-based cipher chip. ASP-DAC (2001)
Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Meng
FeRAM Circuit Technology for System on a Chip. Evolvable Hardware (1999)