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A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture.

Toshihiro KamedaHiroaki KonouraDawood AlnajiarYukio MitsuyamaMasanori HashimotoTakao Onoye
Published in: FPL (2012)
Keyphrases
  • text classification
  • coarse grained
  • reconfigurable architecture
  • fine grained
  • feature selection
  • systolic array
  • protein sequences
  • fault diagnosis
  • high level
  • shared memory
  • parallel architecture