Ryutaro Doi

Publication Activity (10 Years)

Years Active: 2016-2020
Publications (10 Years): 10

Top Topics

Fault Diagnosis

Reconfigurable Architecture

Fpga Implementation

Top Venues

Int. J. Embed. Syst.

Publications

Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto
Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA. DATE (2020)
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC (2020)
Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto
A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2020)
Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Ryutaro Doi, Masanori Hashimoto, Takao Onoye
An analytic evaluation on soft error immunity enhancement due to temporal triplication. Int. J. Embed. Syst. 10 (1) (2018)
Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu
Interconnect Delay Analysis for RRAM Crossbar Based FPGA. ISVLSI (2018)
Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto
Sneak path free reconfiguration of via-switch crossbars based FPGA. ICCAD (2018)
Ryutaro Doi, Masanori Hashimoto
SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA. ISVLSI (2018)
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL (2016)