SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA.

Ryutaro Doi Masanori Hashimoto

Published in: ISVLSI (2018)

Keyphrases

sat encodings
high speed
functional verification
pseudo boolean constraints
sat solvers
model checking
constraint satisfaction problems
field programmable gate array
upper bound
search space
simulated annealing
solving problems