Masayuki Hiromoto

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 33

Top Topics

Nearest Neighbor Classifiers

Parameter Adjustment

Error Tolerance

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

So Hasegawa, Masayuki Hiromoto, Akira Nakagawa, Yuhei Umeda
Improving Predicate Representation in Scene Graph Generation by Self-Supervised Learning. WACV (2023)
Masayuki Hiromoto, Hisanao Akima, Teruo Ishihara, Takuji Yamamoto
SimpleZSL: Extremely Simple and Fast Zero-Shot Learning with Nearest Neighbor Classifiers. IEICE Trans. Inf. Syst. (2) (2022)
Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, Takashi Sato
ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. CoRR (2020)
Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, Takashi Sato
ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. CVPR (2020)
Song Bian, Masayuki Hiromoto, Takashi Sato
Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter. ASP-DAC (2019)
Song Bian, Masayuki Hiromoto, Takashi Sato
DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference. DATE (2019)
Chase Cook, Hengyang Zhao, Takashi Sato, Masayuki Hiromoto, Sheldon X.-D. Tan
GPU-based Ising computing for solving max-cut combinatorial optimization problems. Integr. 69 (2019)
Song Bian, Masayuki Hiromoto, Takashi Sato
Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2019)
Song Bian, Masayuki Hiromoto, Takashi Sato
Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange. DAC (2019)
Yuya Fujita, Masayuki Hiromoto, Takashi Sato
Fast And Robust Heart Rate Estimation From Videos Through Dynamic Region Selection. EMBC (2018)
Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato
Interpolation-Based Object Detection Using Motion Vectors for Embedded Real-Time Tracking Systems. CVPR Workshops (2018)
Masayuki Hiromoto, Motoki Yoshinaga, Takashi Sato
MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato
Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato
Area Efficient Annealing Processor for Ising Model without Random Number Generator. IEICE Trans. Inf. Syst. (2) (2018)
Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
A study on NBTI-induced delay degradation considering stress frequency dependence. ISQED (2018)
Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato
Enhancing the solution quality of hardware ising-model solver via parallel tempering. ICCAD (2018)
Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. ASP-DAC (2018)
Satoshi Yamamori, Masayuki Hiromoto, Takashi Sato
Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Song Bian, Masayuki Hiromoto, Takashi Sato
DWE: decrypting learning with errors with errors. DAC (2018)
Yuya Fujita, Masayuki Hiromoto, Takashi Sato
PARHELIA: Particle Filter-Based Heart Rate Estimation From Photoplethysmographic Signals During Physical Exercise. IEEE Trans. Biomed. Eng. 65 (1) (2018)
Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Efficient circuit failure probability calculation along product lifetime considering device aging. ASP-DAC (2017)
Song Bian, Masayuki Hiromoto, Takashi Sato
SCAM: Secured content addressable memory based on homomorphic encryption. DATE (2017)
Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Identification and Application of Invariant Critical Paths under NBTI Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Comparative study of path selection and objective function in replacing NBTI mitigation logic. ISQED (2017)
Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. DAC (2017)
Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. ACM Great Lakes Symposium on VLSI (2016)
Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Physically unclonable function using RTN-induced delay fluctuation in ring oscillators. ISCAS (2016)
Song Bian, Michihiro Shintani, Zheng Wang, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. ATS (2016)
Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato
Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor. CVPR Workshops (2016)
Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato
Nonlinear delay-table approach for full-chip NBTI degradation prediction. ISQED (2016)
Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. IEICE Trans. Electron. (7) (2015)
Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell. DATE (2015)
Hirofumi Shimizu, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Automation of Model Parameter Estimation for Random Telegraph Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
Variability in device degradations: Statistical observation of NBTI for 3996 transistors. ESSDERC (2014)
Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE (2013)
Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC (2010)
Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura
Dynamic rate control for media streaming in high-speed mobile networks. WCNC (2009)
Masayuki Hiromoto, Ryusuke Miyamoto
Hardware architecture for high-accuracy real-time pedestrian detection with CoHOG features. ICCV Workshops (2009)
Ryoji Kadota, Hiroki Sugano, Masayuki Hiromoto, Hiroyuki Ochi, Ryusuke Miyamoto, Yukihiro Nakamura
Hardware Architecture for HOG Feature Extraction. IIH-MSP (2009)
Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Masayuki Hiromoto, Hiroki Sugano, Ryusuke Miyamoto
Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features. IEEE Trans. Circuits Syst. Video Technol. 19 (1) (2009)
Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye
Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL (2009)
Masayuki Hiromoto, Ryusuke Miyamoto
Cascade Classifier Using Divided CoHOG Features for Rapid Pedestrian Detection. ICVS (2009)
Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
Hot-Swapping architecture extension for mitigation of permanent functional unit faults. FPL (2009)
Masayuki Hiromoto, Kentaro Nakahara, Hiroki Sugano, Yukihiro Nakamura, Ryusuke Miyamoto
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features. CVPR (2007)