Isao Shirakawa

Publication Activity (10 Years)

Years Active: 1977-2016
Publications (10 Years): 1

Top Topics

Image Restoration

Motion Estimation

Super Resolution

Top Venues

Publications

Shinsuke Hara, Takunori Shimazaki, Hiroyuki Okuhata, Isao Shirakawa, Hiroyuki Yomo
A real-time vital sensing system for persons during exercises. ICCE-Berlin (2016)
L. Lin, N. Kawarabayashi, Masahiro Fukui, Isao Shirakawa
Live demonstration: A battery smart sensor for smart grid. APCCAS (2014)
Hiroyuki Okuhata, Rintaro Imai, Masanao Ise, Roberto Y. Omaki, Hajime Nakamura, Shinsuke Hara, Isao Shirakawa
Implementation of dynamic-range enhancement and super-resolution algorithms for medical image processing. ICCE (2014)
Hiroyuki Okuhata, Masanao Ise, Roberto Y. Omaki, Isao Shirakawa
Implementation of super-resolution scaler for Full HD and 4K video. ICCE-Berlin (2013)
Shohei Asakawa, Shuji Tsukiyama, Isao Shirakawa, Shuji Nishi, Tadashi Takeda, Tomoyuki Nagai, Yasushi Kubota
An automatic layout method for timing pulse generator of small LCD driver. ECCTD (2011)
Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa
Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa
Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Gen Fujita, Takaaki Imanaka, Hyunh Van Nhat, Takao Onoye, Isao Shirakawa
Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Zhaohui Guo, Yuuki Nishikawa, Roberto Y. Omaki, Takao Onoye, Isao Shirakawa
A low-complexity FEC assignment scheme for motion JPEG2000 over wireless network. IEEE Trans. Consumer Electron. 52 (1) (2006)
Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa
A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Masanao Ise, Yasuhiro Ogasahara, Takao Onoye, Isao Shirakawa
W-CDMA Channel Codec by Configurable Processors. Intell. Autom. Soft Comput. 12 (3) (2006)
Tomoya Matsumura, Nobuyuki Iwanaga, Takao Onoye, Wataru Kobayashi, Isao Shirakawa, Itthichai Arungsrisangchai
3D sound movement system for embedded applications. ISCAS (5) (2005)
Yukio Mitsuyama, Motoki Kimura, Takao Onoye, Isao Shirakawa
Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Atsushi Kosaka, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa
Design of Ogg Vorbis Decoder System for Embedded Platform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2005)
Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa
Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI (2005)
Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa
A design scheme for sampling switch in active matrix LCD. ECCTD (2005)
Tomoya Matsumura, Nobuyuki Iwanaga, Wataru Kobayashi, Takao Onoye, Isao Shirakawa
Embedded 3D sound movement system based on feature extraction of head-related transfer function. IEEE Trans. Consumer Electron. 51 (1) (2005)
Atsushi Kosaka, Satoshi Yamaguchi, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa
SoC design of Ogg Vorbis decoder using embedded processor. Conf. Computing Frontiers (2004)
Shinichi Maeta, Atsushi Kosaka, Akihisa Yamada, Takao Onoye, Toru Chiba, Isao Shirakawa
C-based hardware design of IMDCT accelerator for Ogg Vorbis decoder. EUSIPCO (2004)
Noriaki Sakamoto, Wataru Kobayashi, Takao Onoye, Isao Shirakawa
Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm. J. Circuits Syst. Comput. 12 (1) (2003)
Shinya Komata, Ablonczy Pal, Noriaki Sakamoto, Wataru Kobayashi, Takao Onoye, Isao Shirakawa
Interactive interface of realtime 3D sound movement for embedded applications. ISCAS (2) (2003)
Motoki Kimura, Morgan Hirosuke Miki, Takao Onoye, Isao Shirakawa
Implementation of Java Accelerator for High-Performance Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Nobuyuki Iwanaga, Wataru Kobayashi, Kazuhiko Furuya, Takao Onoye, Isao Shirakawa
Embedded implementation of acoustic field enhancement for stereo sound sources. IEEE Trans. Consumer Electron. 49 (3) (2003)
Kenji Hontani, Takaaki Imanaka, Gen Fujita, Takao Onoye, Isao Shirakawa
Real-time face object extraction for video phone. ICIP (3) (2003)
Katsuya Nakagawa, Masaru Kawakita, Koji Sato, Mitsuru Minakuchi, Takao Onoye, Toru Chiba, Isao Shirakawa
Object Sharing Scheme for Heterogeneous Environment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2003)
Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai
Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Katsuya Nakagawa, Masaru Kawakita, Koji Sato, Mitsuru Minakuchi, Osamu Tsumori, Keitaro Hanada, Toru Chiba, Isao Shirakawa
OCEAN: Object Communication Environment for Arbitrary Network. ICDCS Workshops (2002)
Yoshihiro Uchida, Masanao Ise, Takao Onoye, Isao Shirakawa, Itthichai Arungsrisangchai
VLSI architecture of digital matched filter and prime interleaver for W-CDMA. ISCAS (3) (2002)
Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
Burst mode: a new acceleration mode for 128-bit block ciphers. CICC (2002)
Kenji Hontani, Takaaki Imanaka, Gen Fujita, Takao Onoye, Isao Shirakawa
Realtime face object extraction algorithm for video phone. APCCAS (1) (2002)
Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai
Parasitic capacitance modeling for multilevel interconnects. APCCAS (1) (2002)
Yoshihiro Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, Takao Onoye, Isao Shirakawa, Toru Chiba
Error correction block based ARQ protocol for wireless digital video transmission. ISCAS (1) (2002)
Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa
Code Efficiency Evaluation for Embedded Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2002)
Hiroshi Mizuno, Hiroyuki Kobayashi, Takao Onoye, Isao Shirakawa
Performance Estimation at Architecture Level for Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Nobuyuki Iwanaga, Wataru Kobayashi, Kazuhiko Furuya, Mamoru Sakamoto, Takao Onoye, Isao Shirakawa
Embedded implementation of acoustic field enhancement for stereo headphones. APCCAS (1) (2002)
T. Kaya, Isao Shirakawa, Ryusuke Miyamoto, Takao Onoye
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process. MTDT (2002)
Roberto Y. Omaki, Gen Fujita, Takao Onoye, Isao Shirakawa
An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2002)
Hiroyuki Okada, Altan-Erdene Shiitev, Hak-Sop Song, Gen Fujita, Takao Onoye, Isao Shirakawa
Error Detection by Digital Watermarking for MPEG-4 Video Coding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2002)
Noriaki Sakamoto, Wataru Kobayashi, Takao Onoye, Isao Shirakawa
DSP implementation of 3D sound localization algorithm for monaural sound source. ICECS (2001)
Morgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa
High Performance Java Hardware Engine and Software Kernel for Embedded Systems. VLSI-SOC (2001)
Makoto Furuie, Takao Onoye, Shuji Tsukiyama, Isao Shirakawa
Two-dimensional array layout for NMOS 4-phase dynamic logic. ICECS (2001)
Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
VLSI architecture of dynamically reconfigurable hardware-based cipher. ISCAS (4) (2001)
Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa
Evaluation of processor code efficiency for embedded systems. ICS (2001)
Roberto Y. Omaki, Yu Dong, Morgan Hirosuke Miki, Makoto Furuie, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa
Realtime wavelet video coder based on reduced memory accessing. ASP-DAC (2001)
Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
A dynamically reconfigurable hardware-based cipher chip. ASP-DAC (2001)
Jianping Fan, Jun Yu, Gen Fujita, Takao Onoye, Lide Wu, Isao Shirakawa
Spatiotemporal segmentation for compact video representation. Signal Process. Image Commun. 16 (6) (2001)
Makoto Furuie, Bao-Yu Song, Yukihiro Yoshida, Takao Onoye, Isao Shirakawa
Layout generation of array cell for NMOS 4-phase dynamic logic (short paper). ASP-DAC (2000)
Roberto Yusi Omaki, Yu Dong, M. Horgan Miki, Makoto Furuie, Shohei Yamada, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa
VLSI implementation of a realtime wavelet video coder. CICC (2000)
Yu Dong, Roberto Y. Omaki, Takao Onoye, Isao Shirakawa
VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder. ICIP (2000)
Hideyuki Fujishima, Yusuke Takemoto, T. Yoneda, Takao Onoye, Isao Shirakawa
Hybrid media-processor core for natural and synthetic video decoding. ISCAS (4) (1999)
Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Meng
FeRAM Circuit Technology for System on a Chip. Evolvable Hardware (1999)
Morgan Hirosuke Miki, Daisuke Taki, Gen Fujita, Takao Onoye, Isao Shirakawa, Toru Fujiwara, Tadao Kasami
Recursive maximum likelihood decoder for high-speed satellite communication. ISCAS (4) (1999)
Hideyuki Fujishima, Yusuke Takemoto, Takao Onoye, Isao Shirakawa
An architecture of a matrix-vector multiplier dedicated to video decoding and three-dimensional computer graphics. IEEE Trans. Circuits Syst. Video Technol. 9 (2) (1999)
Kenji Matsumura, Gen Fujita, Toshihiro Masaki, Isao Shirakawa, Hiroshi Inada
A wireless data processing system constructed of SAW-devices and its applications to medical cares. NSIP (1999)
Akira Nagao, Takashi Kambe, Isao Shirakawa
A layout approach to monolithic microwave IC. ISPD (1998)
Hiroyuki Okuhata, Morgan Hirosuke Miki, Takao Onoye, Isao Shirakawa
A low-power DSP core architecture for low bitrate speech codec. ICASSP (1998)
Akira Nagao, Isao Shirakawa, Takashi Kambe
A layout approach to monolithic microwave IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (12) (1998)
Lijun Luo, Cairong Zou, Zhenya He, Isao Shirakawa
An adaptive quantization algorithm for MPEG-2 video coding. ICASSP (1998)
Takao Onoye, Gen Fujita, Hiroyuki Okuhata, Morgan Hirosuke Miki, Isao Shirakawa
Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing. ASP-DAC (1998)
Gen Fujita, Hiroyuki Okuhata, Morgan Hirosuke Miki, Takao Onoye, Isao Shirakawa
Implementation of H.324 audiovisual codec for mobile computing. CICC (1998)
Yukihiro Yoshida, Bao-Yu Song, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa
An object code compression approach to embedded processors. ISLPED (1997)
Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba
ASK digital demodulation scheme for noise immune infrared data communication. Wirel. Networks 3 (2) (1997)
Hiroyuki Okuhata, Hiroshi Uno, Keiji Kumatani, Isao Shirakawa, Toru Chiba
A Low Power Receiver Architecture for 4 Mbps Infrared Wireless Communication. J. Circuits Syst. Comput. 7 (5) (1997)
Koji Miyanohana, Gen Fujita, Kazuhiro Yanagida, Takao Onoye, Isao Shirakawa
Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visual Communication. J. Circuits Syst. Comput. 7 (5) (1997)
Shun Morikawa, Keisuke Okada, Sumitaka Takeuchi, Isao Shirakawa
A high performance FIR filter dedicated to digital video transmission. ASP-DAC (1997)
Morgan Hirosuke Miki, Gen Fujita, Takao Onoye, Isao Shirakawa
Low-power H.263 video CoDec dedicated to mobile computing. ISLPED (1997)
Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba
Low power architecture for high speed infrared wireless communication system. ISLPED (1997)
Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Itthichai Arungsrisangchai, Hiromitsu Takahashi
Automatic layout recycling based on layout description and linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (8) (1996)
Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe
Optimal Scheduling for Conditional Recource Sharing. ISCAS (1995)
Toshihiro Masaki, Yasuo Morimoto, Takao Onoye, Isao Shirakawa
VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding. IEEE Trans. Circuits Syst. Video Technol. 5 (5) (1995)
Akira Nagao, Chiyoshi Yoshioka, Takashi Kambe, Isao Shirakawa
A layout approach to Monolithic Microwave IC. ASP-DAC (1995)
Hiroshi Uno, Toru Chiba, Keiji Kumatani, Isao Shirakawa
Synthesis and simulation of digital demodulator for infrared data communication. ASP-DAC (1995)
Keisuke Okada, Shun Morikawa, Isao Shirakawa, Sumitaka Takeuchi
A design of high-performance multiplier for digital video transmission. ASP-DAC (1995)
Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa
A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout. ISCAS (1994)
Takayuki Sagishima, Kozo Kimura, Hiroaki Hirata, Tokuzo Kiyohara, Shigeo Asahara, Takao Onoye, Isao Shirakawa
Multi-Threaded Processor for Image Generation. ISCAS (1994)
Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Takashi Kambe
Optimal layout recycling based on graph theoretic linear programming approach. VLSI (1993)
Takashi Shimamoto, Hidetaka Hane, Isao Shirakawa, Shuji Tsukiyama, Shoji Shinoda, Nobuyasu Yui, Nobuyuki Nishiguchi
A distributed routing system for multilayer SOG. EURO-DAC (1992)
Katsunori Tani, Shuji Tsukiyama, Shoji Shinoda, Isao Shirakawa
On area-efficient drawings of rectangular duals for VLSI floor-plan. Math. Program. 52 (1991)
Hiroshi Deguchi, Isao Shirakawa, Koichi Omura, Masato Nishida, Hitoshi Nishimura, Toru Kawata
A tree-structured parallel processing system for image generation by ray tracing. Systems and Computers in Japan 17 (12) (1986)
Hitoshi Nishimura, Hiroshi Ohno, Toru Kawata, Isao Shirakawa, Koichi Omura
LINKS-1: A Parallel Pipelined Multimicrocomputer System for Image Creation ISCA (1983)
Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa
A New Global Router for Gate Array LSIsi. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 (4) (1983)
Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
On the Layering Problem of Multilayer PWB Wiring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 (1) (1983)
Isao Shirakawa, Shin Futagami
A Rerouting Scheme for Single-Layer Printed Wiring Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 (4) (1983)
Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
On the layering problem of multilayer PWB wiring. DAC (1981)
Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki
A Layout System for the Random Logic Portion of an MOS LSI Chip. IEEE Trans. Computers 30 (8) (1981)
Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
On the layering problem of multilayer PWB wiring. Graph Theory and Algorithms (1980)
Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki
A layout system for the random logic portion of MOS LSI. DAC (1980)
Shuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki, Hiromu Ariyoshi
An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset. J. ACM 27 (4) (1980)
Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Toru Chiba, Isao Shirakawa, Hiroshi Ozaki
An Approach to Gate Assignment and Module Placement for Printed Wiring Boards. IEEE Trans. Computers 29 (8) (1980)
Isao Shirakawa
Some comments on permutation layout. Networks 10 (2) (1980)
Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Isao Shirakawa, Hiroshi Ozaki
An approach to gate assignment and module placement for printed wiring boards. DAC (1978)
Shuji Tsukiyama, Mikio Ide, Hiromu Ariyoshi, Isao Shirakawa
A New Algorithm for Generating All the Maximal Independent Sets. SIAM J. Comput. 6 (3) (1977)