Nagisa Ishiura

Publication Activity (10 Years)

Years Active: 1987-2021
Publications (10 Years): 11

Top Topics

Reverse Engineer

Hardware Implementation

Randomly Generated

Top Venues

IPSJ Trans. Syst. LSI Des. Methodol.

A-TEST@ESEC/SIGSOFT FSE

Publications

Wakako Nakano, Yukino Shinohara, Nagisa Ishiura
Full Hardware Implementation of FreeRTOS-Based Real-Time Systems. TENCON (2021)
Kota Kitaura, Nagisa Ishiura
Random testing of compilers' performance based on mixed static and dynamic code comparison. A-TEST@ESEC/SIGSOFT FSE (2018)
Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara
Synthesis of Full Hardware Implementation of RTOS-Based Systems. RSP (2018)
Shogo Takakura, Mitsuyoshi Iwatsuji, Nagisa Ishiura
Extending equivalence transformation based program generator for random testing of C compilers. A-TEST@ESEC/SIGSOFT FSE (2018)
Kagumi Azuma, Nagisa Ishiura, Nobuaki Yoshida, Hiroyuki Kanbara
Distributed memory architecture for high-level synthesis of embedded controllers from Erlang. Erlang Workshop (2017)
Miho Shimizu, Nagisa Ishiura, Sayuri Ota, Wakako Nakano
Speculative execution in distributed controllers for high-level synthesis. RSP (2017)
Yusuke Hibino, Hirofumi Ikeo, Nagisa Ishiura
CF3: Test Suite for Arithmetic Optimization of C Compilers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Kanbara, Hiroyuki Tomiyama
Binary synthesis implementing external interrupt handler as independent module. RSP (2017)
Kazuhiro Nakamura, Nagisa Ishiura
Random testing of C compilers based on test program generation by equivalence transformation. APCCAS (2016)
Atsushi Hashimoto, Nagisa Ishiura
Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs. IPSJ Trans. Syst. LSI Des. Methodol. 9 (2016)
Daisuke Fujiwara, Nagisa Ishiura, Ryo Sakai, Ryo Aoki, Takashi Ogawara
Reverse Engineering from Mainframe Assembly to C Codes in Legacy Migration. IIAI-AAI (2016)
Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura
Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions. IPSJ Trans. Syst. LSI Des. Methodol. 7 (2014)
Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura
Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions. Inf. Media Technol. 9 (4) (2014)
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Nagisa Ishiura
Special Section on VLSI Design and CAD Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama
High-Level Synthesis of Software Function Calls. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Nagisa Ishiura, Tatsuo Watanabe
Datapath oriented codesign method of application specific DSPs using retargetable compiler. APCCAS (1) (2002)
Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe
Thread partitioning method for hardware compiler bach. ASP-DAC (2000)
Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe
Binding and Scheduling Algorithms for Highly Retargetable Compilation. ASP-DAC (1998)
Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe
Optimal Scheduling for Conditional Recource Sharing. ISCAS (1995)
Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima
Fault simulation for multiple faults by Boolean function manipulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (4) (1994)
Nagisa Ishiura, Shuzo Yajima
Linear time fault simulation algorithm using a content addressable memory. EURO-DAC (1992)
Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima
Minimazation of Binary Decision Diagrams Based on Exchanges of Variables. ICCAD (1991)
Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima
Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. DAC (1991)
Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima
Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets. ICCAD (1991)
Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. DAC (1991)
Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. DAC (1990)
Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. DAC (1990)
Nagisa Ishiura, Masayuki Ito, Shuzo Yajima
Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (8) (1990)
Hiroto Yasuura, Nagisa Ishiura
Formal semantics of UDL/I and its applications to CAD/DA tools. ICCD (1990)
Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima
Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram. DAC (1990)
Nagisa Ishiura, Mizuki Takahashi, Shuzo Yajima
Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits. DAC (1989)
Hiroto Yasuura, Nagisa Ishiura
Semantics of a Hardware Design Language for Japanese Standardization. DAC (1989)
Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima
High-Speed Logic Simulation on Vector Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (3) (1987)