Masaharu Imai

Publication Activity (10 Years)

Years Active: 1979-2023
Publications (10 Years): 12

Top Topics

Data Compression

Total Knee Replacement

Histograms Of Oriented Gradients

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Ze Yang, Yimeng Sun, Takao Nakaguchi, Masaharu Imai
EMoDi: Entity-Enhanced Momentum-Difference Contrastive Learning for Semantic-Aware Verification of Scientific Information. ICKG (2023)
Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu
Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2018)
Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi
A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems. J. Inf. Process. 25 (2017)
Fumika Tanabe, Shusuke Yoshimoto, Yuki Noda, Teppei Araki, Takafumi Uemura, Yoshinori Takeuchi, Masaharu Imai, Tsuyoshi Sekitani
Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty. EMBC (2017)
Masaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jørgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez
Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface. ASP-DAC (2017)
Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu
Deformable Part Model Based Arrhythmia Detection Using Time Domain Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2017)
Tomoki Sugiura, Arif Ullah Khan, Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida, Tetsuya Yagi, Masaharu Imai
A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis. BioCAS (2016)
Yuki Hayashida, Yuichi Umehira, Kouki Takatani, Shigetoshi Futami, Seiji Kameda, Takatsugu Kamata, Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai, Tetsuya Yagi
Cortical neural excitations in rats in vivo with using a prototype of a wireless multi-channel microstimulation system. EMBC (2015)
Toshiyo Tamura, Masaki Sekine, Zunyi Tang, Masaki Yoshida, Yoshinori Takeuchi, Masaharu Imai
Preliminary study of a new home healthcare monitoring to prevent the recurrence of stroke. EMBC (2015)
Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai
A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems. BioCAS (2015)
Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai
An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. Inf. Media Technol. 10 (2) (2015)
Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai
An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Masaharu Imai, Yoshio Sugizaki, Koichi Asatani
A New Available Bandwidth Estimation Method Using RTT for a Bottleneck Link. IEICE Trans. Commun. (4) (2014)
Tomoki Sugiura, Shoko Nakatsuka, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai
An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology. BioCAS (2014)
Masaharu Imai, Takayuki Ozawa, Yoshio Sugizaki, Koichi Asatani
Error analysis of an estimation method using RTT for available bandwidth of a bottleneck link. APNOMS (2013)
Masaharu Imai, Yoshio Sugizaki, Koichi Asatani
A new estimation method using RTT for available bandwidth of a bottleneck link. ICOIN (2013)
Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka
Electronic triage system for continuously monitoring casualties at disaster scenes. J. Ambient Intell. Humaniz. Comput. 4 (5) (2013)
Shoko Nakatsuka, Takashi Hamabe, Yoshinori Takeuchi, Masaharu Imai
An efficient lossless data compression method based on exponential-Golomb coding for biomedical information and its implementation using ASIP technology. BioCAS (2013)
Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion. MCSoC (2012)
Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
On-chip Communication Buffer Architecture Optimization Considering Bus Width. MCSoC (2012)
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring. IEICE Trans. Electron. (4) (2012)
Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka
Electronic Triage System: Casualties Monitoring System in the Disaster Scene. 3PGCIC (2011)
Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Automated architecture exploration for low energy reconfigurable AGU. ISOCC (2011)
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato
Biological information sensing technologies for medical, health care, and wellness applications. ASP-DAC (2011)
Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Two-stage configurable decoder model for multiple forward error correction standards. ESTIMedia (2010)
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai
A new compilation technique for SIMD code generation across basic block boundaries. ASP-DAC (2010)
Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. ISCAS (2010)
Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai
Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. ASP-DAC (2009)
Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moniem Wahdan, Masaharu Imai
Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Operation shuffling over cycle boundaries for low energy L0 clustering. ASAP (2008)
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. ASP-DAC (2007)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. ACM Trans. Design Autom. Electr. Syst. 12 (4) (2007)
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. CODES+ISSS (2007)
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi
A Block-Floating-Point Processor for Rapid Application Development. ICASSP (2) (2007)
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC CoRR (2007)
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa
Pack instruction generation for media pUsing multi-valued decision diagram. CODES+ISSS (2006)
Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC (2006)
Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai
Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model. VLSI-SoC (Selected Papers) (2006)
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. DATE (2005)
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Enabling RTOS simulation modeling in a system level design language. ASP-DAC (2005)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. ESTIMedia (2005)
Masaharu Imai, Akira Kitajima
Verification Challenges in Configurable Processor Design with ASIP Meister. CHARME (2005)
H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. ICDCS Workshops (2004)
Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai
S-sequence: a new floorplan representation method preserving room abutment relationships. ISCAS (4) (2004)
Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Synthesizable HDL generation method for configurable VLIW processors. ASP-DAC (2004)
Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE (2004)
Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai
A Code Selection Method for SIMD Processors with PACK Instructions. SCOPES (2003)
Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. ICASSP (2) (2003)
Masaharu Imai
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. ICME (2003)
Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai
Design of Application Specific CISC Using PEAS-III. IEEE International Workshop on Rapid System Prototyping (2002)
Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai
A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai
Design space exploration for DSP applications using the ASIP development system PEAS-III. ICASSP (2002)
Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. ASP-DAC (2001)
Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai
VLSI Implementation of Fractal Image Compression Processor for Moving Pictures. EUROMICRO (2001)
Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi
PEAS-III: An ASIP Design Environment. ICCD (2000)
Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
One language or more?: how can we design an SoC at a system level? ASP-DAC (2000)
Eiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura
Application of FHM-Based Design Method to Scalable 2-D DCT Processor. EUROMICRO (1999)
Takafumi Morifuji, Yoshinori Takeuchi, Masaharu Imai
A programmable processor with multiple functional units and banked registers for general purpose numerical processing. ICASSP (1999)
Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi
A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. ASP-DAC (1998)
Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai
VLSI implementation of a real-time operating system. ASP-DAC (1997)
Masaharu Imai, Eugenio Villar
ASPDAC 1995: HDL synthesizability and interoperability. IEEE Des. Test Comput. 13 (1) (1996)
Takumi Nakano, Andy Utama, Akichika Shiomi, Masaharu Imai, Mitsuyoshi Itabashi
VLSI implementation and evaluation of a real-time operating system. Systems and Computers in Japan 27 (6) (1996)
Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. DAC (1996)
Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. EURO-DAC (1996)
Eugenio Villar, Masaharu Imai
Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC (1995)
Masaharu Imai, Eugenio Villar
Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC (1995)
Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi
A hardware/software codesign method for pipelined instruction set processor using adaptive database. ASP-DAC (1995)
Nguyen-Ngoc Bình, Masaharu Imai, Nobuyuki Hikichi
A hardware/software partitioning algorithm for pipelined instruction set processor. EURO-DAC (1995)
Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi
An ASIP instruction set optimization algorithm with functional module sharing constraint. ICCAD (1993)
Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Jun Sato, Nobuyuki Hikichi, Masaharu Imai
PEAS-I: A hardware/software co-design system for ASIPs. EURO-DAC (1993)
Masaharu Imai, Jun Sato, Alauddin Alomary, Nobuyuki Hikichi
An integer programming approach to instruction implementation method selection problem. EURO-DAC (1992)
Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi
An Integrated Design Environment for Application Specific Integrated Processor. ICCD (1991)
Hiroshi Yamasaki, Tomio Hirata, Masaharu Imai, Toshihide Ibaraki
Computational complexity of the file allocation problem in distributed database systems. Systems and Computers in Japan 19 (3) (1988)
Yoshinao Suzuki, Tomio Hirata, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki
Reconfiguration of a fault-tolerant rectangular systolic array. Systems and Computers in Japan 19 (1) (1988)
Hiromoto Usui, Masafumi Yamashita, Masaharu Imai, Toshihide Ibaraki
Parallel searches of game trees. Systems and Computers in Japan 18 (8) (1987)
Hajime Miura, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki
Implementation of Parallel Prolog on Tree Machines. FJCC (1986)
Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura
The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System. ICDCS (1984)
Masaharu Imai, Yuuji Yoshida, Teruo Fukumura
A Parallel Searching Scheme for Multiprocessor Systems and Its Application to Combinatorial Problems. IJCAI (1979)