A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes.
Nguyen-Ngoc BìnhMasaharu ImaiYoshinori TakeuchiPublished in: ASP-DAC (1998)
Keyphrases
- dynamic programming
- experimental evaluation
- np hard
- recognition algorithm
- preprocessing
- significant improvement
- computational cost
- learning algorithm
- matching algorithm
- detection algorithm
- segmentation algorithm
- low cost
- cost function
- worst case
- high accuracy
- high speed
- optimization algorithm
- objective function
- hardware implementation
- case study
- times faster
- genetic algorithm
- variable sized
- vlsi implementation
- convergence rate
- convex hull
- design process
- computational complexity
- simulated annealing