A hardware/software partitioning algorithm for pipelined instruction set processor.
Nguyen-Ngoc BìnhMasaharu ImaiNobuyuki HikichiPublished in: EURO-DAC (1995)
Keyphrases
- instruction set
- partitioning algorithm
- hardware software
- embedded systems
- instruction set architecture
- computer architecture
- hardware and software
- low cost
- graph partitioning
- high performance computing
- floating point
- application specific
- computer systems
- ibm power processor
- software systems
- general purpose
- field programmable gate array
- multi core processors
- information systems
- pairwise