Murali Jayapala

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 6

Top Topics

Hyperspectral Imaging

Matrix Completion

Top Venues

IEEE Trans. Computational Imaging

Publications

Carolina Blanch Perez del Notario, Steven Thijs, Murali Jayapala
Band Relevance Study of SWIR Hyperspectral Imaging for Material Recycling and Reuse. WHISPERS (2023)
Michiel Vlaminck, Zakaria Bnoulkacem, Gonzalo Luzardo, Hamed Zivariadab, Zohreh Zahiri, Bikram Koirala, Frédéric Mangialetto, Irid Bufi, Ljiljana Platisa, Murali Jayapala, Paul Scheunders, Hiêp Quang Luong
Drone-Based Corrosion Detection on High-Voltage Transmission Towers Using Hyperspectral Imaging. WHISPERS (2023)
Tommaso Giannantonio, Anna Alperovich, Piercosimo Semeraro, Manfredo Atzori, Xiaohan Zhang, Christoph Hauger, Alexander Freytag, Siri Luthman, Roeland Vandebriel, Murali Jayapala, Lien Solie, Steven De Vleeschouwer
Intra-operative Brain Tumor Detection with Deep Learning-Optimized Hyperspectral Imaging. CoRR (2023)
Grigorios Tsagkatakis, Maarten Bloemen, Bert Geelen, Murali Jayapala, Panagiotis Tsakalides
Graph and Rank Regularized Matrix Recovery for Snapshot Spectral Image Demosaicing. IEEE Trans. Computational Imaging 5 (2) (2019)
Grigorios Tsagkatakis, Murali Jayapala, Bert Geelen, Panagiotis Tsakalides
Non-negative Matrix Completion for the Enhancement of Snapshot Mosaic Multispectral Imagery. IMSE (2016)
Prashant Agrawal, Klaas Tack, Bert Geelen, Bart Masschelein, Pablo Mateo Aranda Moran, Andy Lambrechts, Murali Jayapala
Characterization of VNIR Hyperspectral Sensors with Monolithically Integrated Optical Filters. IMSE (2016)
Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Automated architecture exploration for low energy reconfigurable AGU. ISOCC (2011)
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
EMPIRE: Empirical power/area/timing models for register files. Microprocess. Microsystems 33 (4) (2009)
Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest
Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 17 (1) (2009)
Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris
Compilation Technique for Loop Overhead Minimization. DSD (2009)
Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai
Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor
Playing the trade-off game: Architecture exploration using Coffeee. ACM Trans. Design Autom. Electr. Syst. 14 (3) (2009)
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures. IEEE Trans. Computers 58 (3) (2009)
Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. ASP-DAC (2009)
Javed Absar, Praveen Raghavan, Andy Lambrechts, Min Li, Murali Jayapala, Francky Catthoor
Locality optimization in a compiler for wireless applications. Des. Autom. Embed. Syst. 13 (1-2) (2009)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Guillermo Talavera, Murali Jayapala, Jordi Carrabina, Francky Catthoor
Address Generation Optimization for Embedded High-Performance Processors: A Survey. J. Signal Process. Syst. 53 (3) (2008)
Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. VLSI Design (2008)
Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest
Coffee: COmpiler Framework for Energy-Aware Exploration. HiPEAC (2008)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Operation shuffling over cycle boundaries for low energy L0 clustering. ASAP (2008)
Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest
Semi Custom Design: A Case Study on SIMD Shufflers. PATMOS (2007)
Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors. ARCS (2007)
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
Very wide register: an asymmetric register file organization for low power embedded processors. DATE (2007)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. ACM Trans. Design Autom. Electr. Syst. 12 (4) (2007)
Javed Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor
Locality optimization in wireless applications. CODES+ISSS (2007)
Liesbet Van der Perre, Bruno Bougard, Jan Craninckx, Wim Dehaene, Lieven Hollevoet, Murali Jayapala, Pol Marchal, Miguel Miranda, Praveen Raghavan, Thomas Schuster, Piet Wambacq, Francky Catthoor, Peter Vanbekbergen
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. ISSCC (2007)
Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck
Instruction Transfer And Storage Exploration for Low Energy VLIWs. SiPS (2006)
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. DATE (2006)
Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor
Instruction buffering exploration for low energy embedded processors. J. Embed. Comput. 1 (3) (2005)
Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. ASAP (2005)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. ESTIMedia (2005)
Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. IEEE Trans. Computers 54 (6) (2005)
Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck
L0 Cluster Synthesis and Operation Shuffling. PATMOS (2004)
Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal
L0 buffer energy optimization through scheduling and exploration. SAC (2004)
Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll
Design Style Case Study for Embedded Multi Media Compute Nodes. RTSS (2004)
Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal
Instruction buffering exploration for low energy VLIWs with instruction clusters. ASP-DAC (2004)
Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal
Low Power Coarse-Grained Reconfigurable Instruction Set Processor. FPL (2003)
Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor
Instruction Buffering Exploration for Low Energy Embedded Processors. PATMOS (2003)
Paul Marchal, Murali Jayapala, Samuel Xavier de Souza, Peng Yang, Francky Catthoor, Geert Deconinck
Matador: An Exploration Environment for System-Design. J. Circuits Syst. Comput. 11 (5) (2002)
Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. PATMOS (2002)
Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. VLSI Design (2002)
Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins
CRISP: A Template for Reconfigurable Instruction Set Processors. FPL (2001)