Low Power Coarse-Grained Reconfigurable Instruction Set Processor.
Francisco BaratMurali JayapalaTom Vander AaRudy LauwereinsGeert DeconinckHenk CorporaalPublished in: FPL (2003)
Keyphrases
- instruction set
- low power
- coarse grained
- low cost
- fine grained
- embedded systems
- floating point
- power reduction
- power consumption
- high speed
- single chip
- application specific
- computer architecture
- ibm power processor
- shared memory
- protein sequences
- field programmable gate array
- real time
- gate array
- access control
- general purpose
- low power consumption
- high level
- level parallelism
- memory access
- instruction set architecture
- hardware implementation
- massively parallel