Bingfeng Mei

Publication Activity (10 Years)

Years Active: 2001-2010
Publications (10 Years): 0

Publications

Bjorn De Sutter, Osman Allam, Praveen Raghavan, Roeland Vandebriel, Hans Cappelle, Tom Vander Aa, Bingfeng Mei
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors. J. Signal Process. Syst. 61 (2) (2010)
Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest
Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 17 (1) (2009)
Mladen Berekovic, Andreas Kanstein, Bingfeng Mei, Bjorn De Sutter
Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor. Microprocess. Microsystems 33 (4) (2009)
Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei
Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays. LCTES (2008)
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. J. Signal Process. Syst. 51 (3) (2008)
Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. CASES (2007)
Bjorn De Sutter, Bingfeng Mei, T. Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Sukjin Kim
Hardware and a Tool Chain for ADRES. ARC (2006)
Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei
Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. FPL (2005)
Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins
Architecture Exploration for a Reconfigurable Architecture Template. IEEE Des. Test Comput. 22 (2) (2005)
Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein
Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. FPL (2005)
Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde
Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. FPT (2004)
Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. DATE (2004)
Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll
Design Style Case Study for Embedded Multi Media Compute Nodes. RTSS (2004)
Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. DATE (2003)
Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. FPL (2003)
Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins
DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. FPT (2002)
Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. FPL (2001)