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ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.
Bingfeng Mei
Serge Vernalde
Diederik Verkest
Hugo De Man
Rudy Lauwereins
Published in:
FPL (2003)
Keyphrases
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tightly coupled
fine grained
coarse grained
multithreading
digital signal
access control
systolic array
level parallelism
general purpose
instruction set
parallel processing
energy landscape
loosely coupled
functional units
knowledge base