Francisco-Javier Veredas

Publication Activity (10 Years)

Years Active: 2005-2018
Publications (10 Years): 1

Top Topics

Genetic Algorithm Ga

Top Venues

Publications

Francisco-Javier Veredas, Enrique J. Carmona
FPGA Placement Improvement Using a Genetic Algorithm and the Routing Algorithm as a Cost Function. DSD (2018)
Francisco-Javier Veredas, Hans-Jörg Pfleiderer
Power estimation of a LUT-based MPGA. FPT (2006)
Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
LUT-based MPGAs for fast turnaround time conversion flow. ISCAS (2006)
Francisco-Javier Veredas, Hans-Jörg Pfleiderer
Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. FPL (2006)
Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
Regular Routing Architecture for a LUT-based MPGA. ISVLSI (2006)
Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. DATE Designers' Forum (2006)
Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei
Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. FPL (2005)
Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein
Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. FPL (2005)
Francisco-Javier Veredas, Jordi Carrabina
Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. PATMOS (2005)