Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.
Bingfeng MeiFrancisco-Javier VeredasBart MasscheleinPublished in: FPL (2005)
Keyphrases
- reconfigurable architecture
- decoding process
- video codec
- low complexity
- multiview video coding
- systolic array
- video coding standard
- video coding
- mpeg avc
- video transcoding
- motion compensated prediction
- video decoder
- error concealment
- rate control
- coding efficiency
- inter frame
- distributed video coding
- motion estimation
- video compression
- motion compensated
- rate distortion
- bit rate
- rate control algorithm
- video encoder
- coding method
- motion compensation
- computational complexity