Hans-Jörg Pfleiderer

Publication Activity (10 Years)

Years Active: 1979-2009
Publications (10 Years): 0

Publications

Christiane Beuschel, Hans-Jörg Pfleiderer
Fully programmable layered LDPC decoder architecture. EUSIPCO (2009)
Hans-Jörg Pfleiderer, Stefan Lachowicz
Numerically controlled oscillators using linear approximation. FPL (2009)
Stefan Lachowicz, Hans-Jörg Pfleiderer
Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. DELTA (2008)
Christiane Beuschel, Hans-Jörg Pfleiderer
FPGA implementation of a flexible decoder for long LDPC codes. FPL (2008)
Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak
Configurable Blocks for Multi-precision Multiplication. DELTA (2008)
Oliver A. Pfänder, Hans-Jörg Pfleiderer
EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs. FPL (2008)
Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer
Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA. ISCAS (2007)
Shun Zhou, Oliver A. Pfänder, Hans-Jörg Pfleiderer, Amine Bermak
A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier. ICECS (2007)
Francisco-Javier Veredas, Hans-Jörg Pfleiderer
Power estimation of a LUT-based MPGA. FPT (2006)
Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
LUT-based MPGAs for fast turnaround time conversion flow. ISCAS (2006)
Jürgen Rauscher, Hans-Jörg Pfleiderer
Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations. PATMOS (2006)
Markus Buck, Tim Haulick, Hans-Jörg Pfleiderer
Self-calibrating microphone arrays for speech signal acquisition: A systematic approach. Signal Process. 86 (6) (2006)
Francisco-Javier Veredas, Hans-Jörg Pfleiderer
Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. FPL (2006)
Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer
Regular Routing Architecture for a LUT-based MPGA. ISVLSI (2006)
Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. DATE Designers' Forum (2006)
Cristina Tarín, Edgar Teufel, Jesús Picó, Jorge Bondia, Hans-Jörg Pfleiderer
Comprehensive pharmacokinetic model of insulin Glargine and other insulin formulations. IEEE Trans. Biomed. Eng. 52 (12) (2005)
Oliver A. Pfänder, Christophe Layer, Wolfgang Schlecker, Hans-Jörg Pfleiderer
An Interactive Systemc Course Featuring Real-Time Online Compiling and Analysis. EDUTECH (2005)
Christophe Layer, Hans-Jörg Pfleiderer
Efficient Hardware Search Engine for Associative Content Retrieval of Long Queries in Huge Multimedia Databases. ICME (2005)
Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher
3D Chip Stack Technology Using Through-Chip Interconnects. IEEE Des. Test Comput. 22 (6) (2005)
Christophe Layer, Hans-Jörg Pfleiderer
Vertical Sorting Techniques Accelerating Associative Accesses based Information Retrieval Systems. Parallel and Distributed Computing and Networks (2005)
Oliver A. Pfänder, Roland Hacker, Hans-Jörg Pfleiderer
A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. FPL (2004)
Christophe Layer, Hans-Jörg Pfleiderer, Christoph Heer
A scalable compact architecture for the computation of integer binary logarithms through linear approximation. ISCAS (2) (2004)
Christophe Layer, Hans-Jörg Pfleiderer
High Performance Associative Coprocessor Architecture for Advanced Database Searching. Databases and Applications (2004)
Christophe Layer, Hans-Jörg Pfleiderer
A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data. FPL (2004)
Markus Tahedl, Hans-Jörg Pfleiderer
Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. PATMOS (2004)
Edgar Teufel, Marco Kletting, Werner G. Teich, Hans-Jörg Pfleiderer, C. Tarin-Sauer
Modelling the glucose metabolism with backpropagation through time trained Elman nets. NNSP (2003)
Markus Tahedl, Hans-Jörg Pfleiderer
A driver load model for capacitive coupled on-chip interconnect buses. SoC (2003)
Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky
Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach. Discret. Event Dyn. Syst. 12 (3) (2002)
Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg Pfleiderer
Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. FPL (2002)
Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky
Petri Net Based Design and Implementation Methodology for Discrete Event Control Systems. ICATPN (2001)
Stefan Lachowicz, Kamran Eshraghian, M. Hollreiser, Hans-Jörg Pfleiderer
Self-timed MESFET gallium arsenide circuit techniques for a direct digital frequency synthesiser. ISSPA (1999)
Stefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer
Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI. VLSI (1999)
Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer
Large bandwidth BiCMOS operational amplifiers for SC video applications. IEEE J. Solid State Circuits 31 (6) (1996)
Martin Rau, Hans-Jörg Pfleiderer
An ECL to CMOS level converter with complementary bipolar output stage. IEEE J. Solid State Circuits 30 (7) (1995)
Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer
Symbolic pole/zero calculation using SANTAFE. IEEE J. Solid State Circuits 30 (7) (1995)
Gerhard Nebel, U. Kleine, Hans-Jörg Pfleiderer
Large Bandwidth BiCMOS Operational Amplifiers for SC-Video-Applications. ISCAS (1994)
Egon Hörbst, H. Oechslein, Hans-Jörg Pfleiderer
VLSI - Auswirkungen auf konventionelle Rechnerstrukturen. Inform. Spektrum 8 (1) (1985)
G. Grassl, Hans-Jörg Pfleiderer
A function-independent self-test for large programmable logic arrays. Integr. 1 (1) (1983)
Hans-Jörg Pfleiderer, Karl Knauer
Antialiasing Filter with an Improved S/N Ratio. IEEE Trans. Commun. 27 (2) (1979)