Ulrich Ramacher

Publication Activity (10 Years)

Years Active: 1989-2011
Publications (10 Years): 0

Publications

Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Dominik Langen, Jörg Berthold, R. Kramer, A. Schackow, Cyprian Grassmann, Mirko Sauermann, P. Szreder, F. Capar, G. Obradovic, W. Xu, Nico Brüls, Kang Lee, Eugene Weber, Ray Kuhn, John Harrington
Architecture and implementation of a Software-Defined Radio baseband processor. ISCAS (2011)
Ulrich Ramacher
Software-Defined Radio Prospects for Multistandard Mobile Phones. Computer 40 (10) (2007)
Ulrich Ramacher
Challenges and prospects of SDR for mobile phones. ICCD (2007)
Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf
Roundtable: Envisioning the Future for Multiprocessor SoC. IEEE Des. Test Comput. 24 (2) (2007)
Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt
Wireless platforms: GOPS for cents and MilliWatts. DAC (2005)
Marcus Holmberg, David Gelbart, Ulrich Ramacher, Werner Hemmert
Automatic speech recognition with neural spike trains. INTERSPEECH (2005)
Werner Hemmert, Marcus Holmberg, Ulrich Ramacher
Temporal Sound Processing by Cochlear Nucleus Octopus Neurons. ICANN (1) (2005)
Axel Techmer, Hans-Martin Blüthgen, Cyprian Grassmann, J. A. Ulrich Hachmann, Wolfgang Raab, Ulrich Ramacher
Embedded vision platform for video surveillance systems. Electronic Imaging: Image and Video Communications and Processing (2005)
Joachim M. Buhmann, Tilman Lange, Ulrich Ramacher
Image Segmentation by Networks of Spiking Neurons. Neural Comput. 17 (5) (2005)
Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher
3D Chip Stack Technology Using Through-Chip Interconnects. IEEE Des. Test Comput. 22 (6) (2005)
Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher
A low-power memory hierarchy for a fully programmable baseband processor. WMPI (2004)
Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny
Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation. Image Processing: Algorithms and Systems (2004)
Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny
Pulse coupled neural networks with adaptive synapses for image segmentation. ARCS Workshops (2004)
Arne Heittmann, Ulrich Ramacher
Correlation-based feature detection using pulsed neural networks. NNSP (2003)
Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer
100 GOPS vision processor for automotive applications. SIGARCH Comput. Archit. News 31 (1) (2003)
Hans-Martin Blüthgen, Cyprian Grassmann, Wolfgang Raab, Ulrich Ramacher
A programmable platform for software-defined radio. SoC (2003)
Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer
A 100-GOPS Programmable Processor for Vehicle Vision Systems. IEEE Des. Test Comput. 20 (1) (2003)
Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, D. Matolini, René Schüffny
Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity. NNSP (2002)
Arne Heittmann, Ulrich Ramacher, Daniel Matolin, Jörg Schreiter, René Schüffny
An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. ICANN (2002)
Ulrich Ramacher
Application Specific Embedded Processors for Next Generation Communication Systems. ICCD (2002)
Chr. Werner, R. Göttsche, A. Wörner, Ulrich Ramacher
Crosstalk noise in future digital CMOS circuits. DATE (2001)
Ulrich Ramacher, Wolfgang Raab, Wolfgang Kabatzke
Prototyp eines Bildrechners für Echtzeitbildverarbeitung in Industrie- und Medientechnik. PEARL (1999)
Ulrich Ramacher
SEE-1 - A Vision System for Use in Real World Environments. ICANN (1996)
Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer
SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. IPPS (1995)
Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder
Architecture and VLSI Design of a VLSI Neural Signal Processor. ISCAS (1993)
Ulrich Ramacher, Peter Schildberg
Recent Developments In Neurodynamics And Their Impact On The Design Of Neuro-Chips. Int. J. Neural Syst. 4 (4) (1993)
Ulrich Ramacher
Hamiltonian dynamics of neural networks. Neural Networks 6 (4) (1993)
Ulrich Ramacher, Wolfgang Raab, Joachim K. Anlauf, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Reinhard Männer, Joachim Gläß, Andreas Wurz
Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. Int. J. Neural Syst. 4 (4) (1993)
Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar
Design of a general-purpose neural signal processor. Neurocomputing 5 (1) (1993)
Ulrich Ramacher, Jörg Beichter, Nico Brüls
A general-purpose signal processor architecture for neurocomputing and preprocessing applications. J. VLSI Signal Process. 6 (1) (1993)
Ulrich Ramacher
SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine. J. Parallel Distributed Comput. 14 (3) (1992)
Karl Goser, Ulrich Ramacher
Mikroelektronische Realisierung von künstlichen neuronalen Netzen / Microelectronic Realizations of artificial neural networks. it Inf. Technol. 34 (4) (1992)
Ulrich Ramacher, Wolfgang Raab
Fine-grain system architectures for systolic emulation of neural algorithms. ASAP (1990)
Matthias Wesseling, Ulrich Ramacher, Karl Goser
Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area. Fehlertolerierende Rechensysteme (1989)