Heinrich Klar

Publication Activity (10 Years)

Years Active: 1993-2016
Publications (10 Years): 1

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Implementation Issues

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Publications

Adel Fatemi, Heinrich Klar, Friedel Gerfers
Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm. ISCAS (2016)
Yi Yin, Heinrich Klar, Peter Wennekers
A cascade 3-1-1 multibit ΣΔ A/D modulator with reduced sensitivity to non-idealities. ISCAS (4) (2005)
Yi Yin, Heinrich Klar, Peter Wennekers
A novel broadband cascade sigma-delta analog-to-digital converter. Circuits, Signals, and Systems (2004)
Nasser Mehrtash, Dietmar Jung, Heinrich Klar
Image preprocessing with dynamic synapses. Neural Comput. Appl. 12 (1) (2003)
Nasser Mehrtash, Dietmar Jung, Heik Heinrich Hellmich, Tim Schönauer, Vi Thanh Lu, Heinrich Klar
INN): a system approach. IEEE Trans. Neural Networks 14 (5) (2003)
Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar
NeuroPipe-Chip: A digital neuro-processor for spiking neural networks. IEEE Trans. Neural Networks 13 (1) (2002)
Martin Schäfer, Tim Schönauer, Carsten Wolff, Georg Hartmann, Heinrich Klar, Ulrich Rückert
Simulation of spiking neural networks -- architectures and implementations. Neurocomputing 48 (1-4) (2002)
Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar
Simulation of a Digital Neuro-Chip for Spiking Neural Networks. IJCNN (4) (2000)
Martin Ehlert, Heinrich Klar
A 12-bit medium-time analog storage device in a CMOS standard process. IEEE J. Solid State Circuits 33 (7) (1998)
Ulrich Roth, Marc Walker, Arne Hilmann, Heinrich Klar
Dynamic Path Planning with Spiking Neural Networks. IWANN (1997)
Axel Jahnke, Tim Schönauer, Ulrich Roth, K. Mohraz, Heinrich Klar
Simulation of Spiking Neural Networks on Different Hardware Platforms. ICANN (1997)
Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar
A New Bio-inspired Algorithm for Early Vision Edge Detection and Image Segmentation. IWANN (1997)
Ulrich Roth, Axel Jahnke, Heinrich Klar
On-Line Hebbian Learning for Spiking Neurons: Architecture of the Weight-Unit of NESPINN. ICANN (1997)
Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar
An Improved Multiplexed Resistive Network for Analog Image Preprocessing. ICANN (1997)
Jorg-Michael Green, Heinrich Klar
A CMOS gate array architecture for digital signal processing applications. IEEE J. Solid State Circuits 31 (3) (1996)
S. R. Kadivar, Doris Schmitt-Landsiedel, Heinrich Klar
A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. ICCAD (1995)
Ulrich Roth, Axel Jahnke, Heinrich Klar
Hardware Requirements for Spike-Processing Neural Networks. IWANN (1995)
O. Salomon, Jorg-Michael Green, Heinrich Klar
General algorithms for a simplified addition of 2's complement numbers. IEEE J. Solid State Circuits 30 (7) (1995)
T. Juhnke, Heinrich Klar
Calculation of the soft error rate of submicron CMOS logic circuits. IEEE J. Solid State Circuits 30 (7) (1995)
O. Salomon, Heinrich Klar
Self-Timed Fully Pipelined Multipliers. Asynchronous Design Methodologies (1993)
Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar
Design of a general-purpose neural signal processor. Neurocomputing 5 (1) (1993)