Calculation of the soft error rate of submicron CMOS logic circuits.
T. JuhnkeHeinrich KlarPublished in: IEEE J. Solid State Circuits (1995)
Keyphrases
- error rate
- logic circuits
- low power
- vlsi circuits
- power consumption
- high speed
- low cost
- mixed signal
- power dissipation
- cmos technology
- test set
- functional decomposition
- gate array
- lower error rates
- logic synthesis
- tunnel diode
- digital signal processing
- face recognition
- parallel processing
- equal error rate
- signal processing
- false discovery rate