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A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier.

Shun ZhouOliver A. PfänderHans-Jörg PfleidererAmine Bermak
Published in: ICECS (2007)
Keyphrases
  • vlsi architecture
  • vlsi implementation
  • low power
  • hardware implementation
  • low complexity
  • low cost
  • real time
  • neural network
  • image processing
  • computational complexity
  • signal processing