Login / Signup
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
Ittetsu Taniguchi
Murali Jayapala
Praveen Raghavan
Francky Catthoor
Keishi Sakanushi
Yoshinori Takeuchi
Masaharu Imai
Published in:
ASP-DAC (2009)
Keyphrases
</>
low energy
embedded processors
electron microscopy
minimum energy
single chip
real time
protein folding
image processing
high level
power consumption