Login / Signup
Keishi Sakanushi
Publication Activity (10 Years)
Years Active: 1998-2013
Publications (10 Years): 0
Top Topics
Disaster Relief
Monitoring System
High Speed
Situational Awareness
Top Venues
MCSoC
J. Ambient Intell. Humaniz. Comput.
IEICE Trans. Electron.
</>
Publications
</>
Keishi Sakanushi
,
Takuji Hieda
,
Taichiro Shiraishi
,
Yasumasa Ode
,
Yoshinori Takeuchi
,
Masaharu Imai
,
Teruo Higashino
,
Hiroshi Tanaka
Electronic triage system for continuously monitoring casualties at disaster scenes.
J. Ambient Intell. Humaniz. Comput.
4 (5) (2013)
Sho Ninomiya
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion.
MCSoC
(2012)
Salita Sombatsiri
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
On-chip Communication Buffer Architecture Optimization Considering Bus Width.
MCSoC
(2012)
Hirofumi Iwato
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring.
IEICE Trans. Electron.
(4) (2012)
Keishi Sakanushi
,
Takuji Hieda
,
Taichiro Shiraishi
,
Yasumasa Ode
,
Yoshinori Takeuchi
,
Masaharu Imai
,
Teruo Higashino
,
Hiroshi Tanaka
Electronic Triage System: Casualties Monitoring System in the Disaster Scene.
3PGCIC
(2011)
Ittetsu Taniguchi
,
Ayataka Kobayashi
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2011)
Ittetsu Taniguchi
,
Murali Jayapala
,
Praveen Raghavan
,
Francky Catthoor
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Automated architecture exploration for low energy reconfigurable AGU.
ISOCC
(2011)
Masaharu Imai
,
Yoshinori Takeuchi
,
Keishi Sakanushi
,
Hirofumi Iwato
Biological information sensing technologies for medical, health care, and wellness applications.
ASP-DAC
(2011)
Ittetsu Taniguchi
,
Ayataka Kobayashi
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Two-stage configurable decoder model for multiple forward error correction standards.
ESTIMedia
(2010)
Masaharu Imai
,
Yoshinori Takeuchi
,
Keishi Sakanushi
,
Nagisa Ishiura
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).
IPSJ Trans. Syst. LSI Des. Methodol.
3 (2010)
Hirofumi Iwato
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions.
IPSJ Trans. Syst. LSI Des. Methodol.
3 (2010)
Hassan A. Youness
,
Abdel-Moniem Wahdan
,
Mohammed Hassan
,
Ashraf Salem
,
Mohammed Moness
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm.
ISCAS
(2010)
Takuji Hieda
,
Hiroaki Tanaka
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2009)
Ittetsu Taniguchi
,
Murali Jayapala
,
Praveen Raghavan
,
Francky Catthoor
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
ASP-DAC
(2009)
Hassan A. Youness
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Ashraf Salem
,
Abdel-Moniem Wahdan
,
Masaharu Imai
Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(4) (2009)
Hiroaki Tanaka
,
Yoshinori Takeuchi
,
Keishi Sakanushi
,
Masaharu Imai
,
Hiroki Tagawa
,
Yutaka Ota
,
Nobu Matsumoto
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2007)
Takeshi Shiro
,
Masaaki Abe
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units.
ASP-DAC
(2007)
Hirofumi Iwato
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
A low power VLIW processor generation method by means of extracting non-redundant activation conditions.
CODES+ISSS
(2007)
Hiroaki Tanaka
,
Yoshinori Takeuchi
,
Keishi Sakanushi
,
Masaharu Imai
,
Shiro Kobayashi
A Block-Floating-Point Processor for Rapid Application Development.
ICASSP (2)
(2007)
M. Abdelsalam Hassan
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
CoRR
(2007)
Hiroaki Tanaka
,
Yoshinori Takeuchi
,
Keishi Sakanushi
,
Masaharu Imai
,
Yutaka Ota
,
Nobu Matsumoto
,
Masaki Nakagawa
Pack instruction generation for media pUsing multi-valued decision diagram.
CODES+ISSS
(2006)
Ittetsu Taniguchi
,
Kyoko Ueda
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.
VLSI-SoC
(2006)
Ittetsu Taniguchi
,
Keishi Sakanushi
,
Kyoko Ueda
,
Yoshinori Takeuchi
,
Masaharu Imai
Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.
VLSI-SoC (Selected Papers)
(2006)
M. Abdelsalam Hassan
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC.
DATE
(2005)
M. Abdelsalam Hassan
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Enabling RTOS simulation modeling in a system level design language.
ASP-DAC
(2005)
H. M. AbdElSalam
,
Shinsuke Kobayashi
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation.
ICDCS Workshops
(2004)
Yohei Ishimaru
,
Keishi Sakanushi
,
Shinsuke Kobayashi
,
Yoshinori Takeuchi
,
Masaharu Imai
S-sequence: a new floorplan representation method preserving room abutment relationships.
ISCAS (4)
(2004)
Yuki Kobayashi
,
Shinsuke Kobayashi
,
Koji Okuda
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Synthesizable HDL generation method for configurable VLIW processors.
ASP-DAC
(2004)
Kyoko Ueda
,
Keishi Sakanushi
,
Yoshinori Takeuchi
,
Masaharu Imai
Architecture-Level Performance Estimation for IP-Based Embedded Systems.
DATE
(2004)
Hiroaki Tanaka
,
Shinsuke Kobayashi
,
Yoshinori Takeuchi
,
Keishi Sakanushi
,
Masaharu Imai
A Code Selection Method for SIMD Processors with PACK Instructions.
SCOPES
(2003)
Changwen Zhuang
,
Keishi Sakanushi
,
Liyan Jin
,
Yoji Kajitani
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost.
ASP-DAC
(2003)
Kazuya Wakata
,
Hiroaki Saito
,
Kunihiro Fujiyoshi
,
Keishi Sakanushi
,
Takayuki Obata
,
Chikaaki Kodama
An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2003)
Keishi Sakanushi
,
Zhonglin Wu
,
Yoji Kajitani
Recognition of Floorplan by Parametric BSG for Reuse of Layout Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(4) (2002)
Changwen Zhuang
,
Yoji Kajitani
,
Keishi Sakanushi
,
Liyan Jin
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees.
DATE
(2002)
Hiroaki Saito
,
Kazuya Wakata
,
Kunihiro Fujiyoshi
,
Keishi Sakanushi
,
Takayuki Obata
An improved method of convex-shaped block packing based on sequence-pair [VLSI layout].
APCCAS (2)
(2002)
Keishi Sakanushi
,
Shigetoshi Nakatake
,
Yoji Kajitani
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks.
ICCAD
(1998)
Shigetoshi Nakatake
,
Keishi Sakanushi
,
Yoji Kajitani
,
Masahiro Kawakita
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.
ICCAD
(1998)