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A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts.
Nguyen-Ngoc Bình
Masaharu Imai
Akichika Shiomi
Nobuyuki Hikichi
Published in:
DAC (1996)
Keyphrases
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partitioning algorithm
hardware software
hardware and software
hw sw
embedded systems
graph partitioning
multi core processors
design methodology
high performance computing
low cost
hardware design
relational databases
data processing
field programmable gate array