Eugenio Villar

Publication Activity (10 Years)

Years Active: 1992-2023
Publications (10 Years): 19

Top Topics

Design Space Exploration

Embedded Systems

Enabling Technologies

Top Venues

Microprocess. Microsystems

Publications

Héctor Posadas, José Luis Vázquez, Eugenio Villar
Automatic code generation from UML for data memory optimization in microcontrollers. DCIS (2023)
Réda Nouacer, Mahmoud Hussein, Paul Detterer, Eugenio Villar, Fernando Herrera, Carlo Tieri, Emmanuel Grolleau
Towards a European Network of Enabling Technologies for Drones. DroneSE/RAPIDO@HiPEAC (2023)
Javier Merino, Raul Gomez, Hector Posadas, Eugenio Villar
Multilevel host-compiled simulation framework for ROS-based UAV services using ArduCopter. DCIS (2021)
Javier Merino, Raul Gomez, Hector Posadas, Eugenio Villar
Modeling and Performance Estimation of Robotic Systems using ROS: Application to drone-based Services. FDL (2021)
Mahmoud Hussein, Réda Nouacer, Federico Corradi, Yassine Ouhammou, Eugenio Villar, Carlo Tieri, Rodrigo Castiñeira
Key technologies for safe and autonomous drones. Microprocess. Microsystems 87 (2021)
Héctor Posadas, Javier Merino, Eugenio Villar
Data flow analysis from UML/MARTE models based on binary traces. DCIS (2020)
Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Hector Posadas, Javier Merino, Eugenio Villar
Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow. DSD (2020)
Eugenio Villar, Javier Merino, Hector Posadas, Rafik Henia, Laurent Rioux
Mega-modeling of complex, distributed, heterogeneous CPS systems. Microprocess. Microsystems 78 (2020)
Mahmoud Hussein, Réda Nouacer, Yassine Ouhammou, Eugenio Villar, Federico Corradi, Carlo Tieri, Rodrigo Castiñeira
Key Enabling Technologies for Drones. DSD (2020)
Héctor Posadas, Eugenio Villar, Manuel Sanchez-Renedo
Accelerating Host-Compiled Simulation by Modifying IR Code: Industrial application in the spatial domain. DCIS (2019)
Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Emanuele Vitali, Davide Zoni, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Nima Khalilzad, Davide Quaglia
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocess. Microsystems 51 (2017)
Hector Posadas, Luis Diaz, Eugenio Villar
Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy. DSD (2017)
Houcine Hassan, Laurence T. Yang, Jason Xue, Eugenio Villar
Special issue on: "Heterogeneous architectures for Cyber-physical systems (HACPS)". Microprocess. Microsystems 52 (2017)
Ralph Görgen, Kim Grüttner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Davide Quaglia
CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties. DSD (2016)
Hector Posadas, Eugenio Villar
Using Professional Resources for Teaching Embedded SW Development. Rev. Iberoam. de Tecnol. del Aprendiz. 11 (4) (2016)
Fernando Herrera, Pablo Peñil, Eugenio Villar
Enhancing analysability and time predictability in UML/MARTE component-based application models. FDL (2015)
Jiafu Wan, Chin-Feng Lai, Shiwen Mao, Eugenio Villar, Subhas Mukhopadhyay
Innovative circuit and system design methodologies for green cyber-physical systems. Microprocess. Microsystems 39 (8) (2015)
Fernando Herrera, Pablo Peñil, Eugenio Villar
A model-based, single-source approach to design-space exploration and synthesis of mixed-criticality systems. SCOPES (2015)
Héctor Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar
Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics. J. Syst. Archit. 61 (8) (2015)
Alejandro Nicolás, Pablo Peñil, Héctor Posadas, Eugenio Villar
Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse. DSD (2014)
Héctor Posadas, Alejandro Nicolás, Pablo Peñil, Eugenio Villar, Florian Broekaert, Michel Bourdellès, Albert Cohen, Mihai T. Lazarescu, Luciano Lavagno, Andrei Sergeevich Terechko, Miguel Glassee, Manuel Prieto
Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project. Microprocess. Microsystems 38 (8) (2014)
Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia, Gianluca Palermo
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems. J. Syst. Archit. 60 (1) (2014)
Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia, Hector Posadas, Eugenio Villar
A framework for design space exploration and performance analysis of networked embedded systems. RAPIDO (2014)
Héctor Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar
Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation. Microelectron. J. 45 (10) (2014)
Hector Posadas, Eugenio Villar, Florian Broekaert, Michel Bourdellès, Albert Cohen, Antoniu Pop, Nhat Minh Lê, Adrien Guatto, Mihai T. Lazarescu, Luciano Lavagno, Andrei Sergeevich Terechko, Miguel Glassee, Daniel Calvo, Eduardo de las Heras
EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications. DSD (2013)
Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration. Microprocess. Microsystems 37 (8-C) (2013)
Rodrigo Fernández, Hector Posadas, Eugenio Villar
Early Performance Evaluation of Multi-OS Embedded Platforms Using Native Simulation. DSD (2013)
Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia
A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models. CODES+ISSS (2012)
Fernando Herrera, Iñigo Ugarte, Eugenio Villar
Towards automated implementation of adaptive systems from abstract SystemC specifications - From SystemC adaptive processes to embedded software and to synthesizable hardware descriptions. Des. Autom. Embed. Syst. 16 (3) (2012)
Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia
The COMPLEX Eclipse framework for UML/MARTE specification and design space exploration of embedded systems. DASIP (2012)
Fernando Herrera, Hector Posadas, Eugenio Villar, Daniel Calvo
Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE. DSD (2012)
Fernando Herrera, Pablo Peñil, Hector Posadas, Eugenio Villar
A model-driven methodology for the development of SystemC executable environments. FDL (2012)
Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia
COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration. DSD (2012)
Pablo Peñil, Héctor Posadas, Alejandro Nicolás, Eugenio Villar
Automatic synthesis from UML/MARTE models using channel semantics. ACES-MB@MoDELS (2012)
Julio Gómez López, Eugenio Villar, Gabriel Molero, Alejandro Cama-Pinto
Evaluation of High Performance Clusters in Private Cloud Computing Environments. DCAI (2012)
Fernando Herrera, Pablo Peñil, Hector Posadas, Eugenio Villar
Model-Driven Methodology for the Development of Multi-level Executable Environments. FDL (Selected Papers) (2012)
Fernando Herrera, Eugenio Villar
A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation. FDL (2011)
Fernando Herrera, Eugenio Villar, Philipp A. Hartmann
Systemc refinement of abstract adaptive processes for implementation into Dynamically Reconfigurable Hardware. FDL (2011)
Hector Posadas, Eugenio Villar, Dominique Ragot, Marcos Martínez
Early, time-approximate modeling of multi-OS. linux platforms in a systemC co-simulation environment. Comput. Syst. Sci. Eng. 26 (6) (2011)
Daniel Calvo, Pablo González, Luis Diaz, Hector Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico Macii
A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design. J. Low Power Electron. 7 (1) (2011)
Hector Posadas, Luis Diaz, Eugenio Villar
Fast data-cache modeling for native co-simulation. ASP-DAC (2011)
Pablo Peñil, Hector Posadas, Eugenio Villar
Formal Modeling for UML/MARTE Concurrency Resources. ICECCS (2010)
Pablo Peñil, Fernando Herrera, Eugenio Villar
Formal Foundations for MARTE-SystemC Interoperability. FDL (2010)
Wolfgang Müller, Da He, Fabian Mischkalla, Arthur Wegele, Paul Whiston, Pablo Peñil, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda
The SATURN Approach to SysML-Based HW/SW Codesign. ISVLSI (2010)
Eugenio Villar, Fernando Herrera, Víctor Fernández
Formal Support for Untimed SystemC Specifications: Application to High-level Synthesis. FDL (2010)
Pablo Peñil, Julio L. Medina, Hector Posadas, Eugenio Villar
Generating heterogeneous executable specifications in SystemC from UML/MARTE models. Innov. Syst. Softw. Eng. 6 (1-2) (2010)
Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez
Fast instruction cache modeling for approximate timed HW/SW co-simulation. ACM Great Lakes Symposium on VLSI (2010)
Wolfgang Müller, Da He, Fabian Mischkalla, Arthur Wegele, Adrian Larkham, Paul Whiston, Pablo Peñil, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda
The SATURN Approach to SysML-Based HW/SW Codesign. ISVLSI (Selected papers) (2010)
Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Hao Zhang, Shibin Tang
MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures. ISVLSI (Selected papers) (2010)
Sara Real, Hector Posadas, Eugenio Villar
L2 Cache Modeling based on address modification for Native Co-Simulation in SystemC. SIES (2010)
Roberto Varona-Gomez, Eugenio Villar
AADS+: AADL Simulation Including the Behavioral Annex. ICECCS (2010)
Hector Posadas, Eugenio Villar, Dominique Ragot, Marcos Martínez
Early Modeling of Linux-Based RTOS Platforms in a SystemC Time-Approximate Co-simulation Environment. ISORC (2010)
Hector Posadas, Eugenio Villar
Modeling Separate Memory Spaces in Native Co-simulation with SystemC for Design Space Exploration. ARCS Workshops (2010)
Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Hao Zhang, Shibin Tang
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures. ISVLSI (2010)
Hector Posadas, Eugenio Villar
Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation. IESS (2009)
Fernando Herrera, Eugenio Villar
Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specifications. FDL (2009)
Roberto Varona-Gomez, Eugenio Villar
AADL Simulation and Performance Analysis in SystemC. ICECCS (2009)
Fernando Herrera, Eugenio Villar, Philipp A. Hartmann
Specification of Adaptive HW/SW Systems in SystemC. FDL (2008)
Christoph Grimm, Axel Jantsch, Sandeep Kumar Shukla, Eugenio Villar
C-Based Design of Heterogeneous Embedded Systems. EURASIP J. Embed. Syst. 2008 (2008)
Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel
Heterogeneous System-level Specification Using SystemC. DATE (2008)
Markus Damm, Jan Haase, Christoph Grimm, Fernando Herrera, Eugenio Villar
Bridging MoCs in SystemC Specifications of Heterogeneous Systems. EURASIP J. Embed. Syst. 2008 (2008)
Fernando Herrera, Eugenio Villar
A framework for heterogeneous specification and design of electronic embedded systems in SystemC. ACM Trans. Design Autom. Electr. Syst. 12 (3) (2007)
Hector Posadas, David Quijano, Eugenio Villar, Marcos Martínez
Protocol Bus Modeling using inheritance with TLM2.0. FDL (2007)
Fernando Herrera, Eugenio Villar, Christoph Grimm, Markus Damm, Jan Haase
A general approach to the interoperability of HetSC and SystemC-AMS. FDL (2007)
Eduardo de las Heras, Eugenio Villar
Specification for SystemC-AADL interoperability. WISES (2007)
Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, Florian Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, Marcos Martínez
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. FPL (2007)
Hector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar, Francisco Blasco
POSIX modeling in SystemC. ASP-DAC (2006)
Fernando Herrera, Eugenio Villar
Extension of the SystemC Kernel for Simulation Coverage. FDL (2006)
Fernando Herrera, Eugenio Villar
A framework for embedded system specification under different models of computation in SystemC. DAC (2006)
Fernando Herrera, Eugenio Villar
Mixing Synchronous Reactive and Untimed Models of Computation. FDL (2005)
Hector Posadas, Jesús Ádamez, Eugenio Villar, Francisco Blasco, F. Escuder
RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model. Des. Autom. Embed. Syst. 10 (4) (2005)
Fernando Herrera, Pablo Sánchez, Eugenio Villar
Heterogeneous System-Level Specification in SystemC. FDL (2004)
Hector Posadas, Fernando Herrera, Pablo Sánchez, Eugenio Villar, Francisco Blasco
System-Level Performance Analysis in SystemC. DATE (2004)
Hector Posadas, Fernando Herrera, Víctor Fernández, Pablo Sánchez, Eugenio Villar, Francisco Blasco
Single Source Design Environment for Embedded Systems Based on SystemC. Des. Autom. Embed. Syst. 9 (4) (2004)
Fernando Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar
Systemic Embedded Software Generation from SystemC. DATE (2003)
Fernando Herrera, Pablo Sánchez, Eugenio Villar
Modeling of CSP, KPN and SR Systems with SystemC. FDL (2003)
Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, J. Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong
C/C++: progress or deadlock in system-level specification. DATE (2001)
Giulio Gorla, Eduard Moser, Wolfgang Nebel, Eugenio Villar
System Specification Experiments on a Common Benchmark. IEEE Des. Test Comput. 17 (3) (2000)
Adrian López, Maite Veiga, Eugenio Villar
Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL. Ada-Europe (1999)
Pedro Tabuenca, Pablo Sánchez, Eugenio Villar
An algorithm for clock cycle selection in behavioral synthesis. J. Syst. Archit. 44 (9-10) (1998)
Masaharu Imai, Eugenio Villar
ASPDAC 1995: HDL synthesizability and interoperability. IEEE Des. Test Comput. 13 (1) (1996)
Manfred Selz, Wolfgang Ecker, Eugenio Villar
VHDL synthesis description portability: The need for Level synthesis subsets. J. Syst. Archit. 42 (2) (1996)
Eugenio Villar, Masaharu Imai
Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC (1995)
Masaharu Imai, Eugenio Villar
Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC (1995)
E. Randon, P. Sanchez, Eugenio Villar
ESP, a structure synthesis program. Microprocess. Microprogramming 34 (1-5) (1992)