High-Speed Logic Simulation on Vector Processors.

Nagisa Ishiura Hiroto Yasuura Shuzo Yajima

Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1987)

Keyphrases

high speed
parallel algorithm
simulation model
low power
feature vectors
logic programming
single processor
asynchronous circuits
real time
parallel computers
defeasible logic
classical logic
automated reasoning
simulation environment
parallel computing
modal logic
simulation study
data sets