A Layout System for the Random Logic Portion of an MOS LSI Chip.
Isao ShirakawaNoboru OkudaTakashi HaradaSadahiro TaniHiroshi OzakiPublished in: IEEE Trans. Computers (1981)
Keyphrases
- chip design
- micron cmos
- latent semantic indexing
- flip flops
- high speed
- random access memory
- logic programming
- low cost
- high density
- modal logic
- multi valued
- classical logic
- physical design
- power dissipation
- asynchronous circuits
- programmable logic
- host computer
- vector space
- digital circuits
- layout design
- analog vlsi
- application specific integrated circuits
- neural network