A low-power DSP core architecture for low bitrate speech codec.
Hiroyuki OkuhataMorgan Hirosuke MikiTakao OnoyeIsao ShirakawaPublished in: ICASSP (1998)
Keyphrases
- low power
- bit rate
- digital signal processing
- video coding
- bitstream
- low power consumption
- high speed
- power consumption
- inter frame
- low cost
- coding method
- low bit rate
- video quality
- rate distortion
- cmos technology
- bit allocation
- video codec
- mixed signal
- visual quality
- motion vectors
- intra frame
- rate control
- image quality
- real time
- macroblock
- video compression
- motion estimation
- coding scheme
- computational complexity
- motion compensation
- coding efficiency
- scalable video coding
- compression algorithm
- motion compensated
- rate allocation
- packet loss
- video sequences
- data flow
- compression efficiency
- storage devices
- error concealment
- distributed video coding
- scalable video
- error resilient
- video transmission
- bit plane
- frame rate
- error resilience
- image compression
- power dissipation
- signal processing
- video streaming