C-based hardware design of IMDCT accelerator for Ogg Vorbis decoder.
Shinichi MaetaAtsushi KosakaAkihisa YamadaTakao OnoyeToru ChibaIsao ShirakawaPublished in: EUSIPCO (2004)
Keyphrases
- hardware design
- field programmable gate array
- hardware implementation
- error concealment
- embedded systems
- fpga hardware
- low complexity
- parallel implementation
- image processing algorithms
- hardware software
- parallel computing
- video codec
- artificial intelligence
- decoding process
- real time
- motion estimation
- image processing
- neural network
- distributed video coding