Toyohiko Yoshida

Publication Activity (10 Years)

Years Active: 1988-2002
Publications (10 Years): 0

Publications

Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa
Code Efficiency Evaluation for Embedded Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2002)
Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa
Evaluation of processor code efficiency for embedded systems. ICS (2001)
Satoshi Kumaki, Tetsuya Matsumura, Kamya Ishihara, Hiroshi Segawa, Kiyofumi Kawamoto, Hideo Ohira, Toshiaki Shimada, Hidenori Sato, Takashi Hattori, Tetsuro Wada, Hiroshi Honma, Tetsuya Watanabe, Hisakazu Sato, Ken'ichi Asano, Toyohiko Yoshida
A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores. CICC (1999)
Atsuo Hanami, Stefan Scotzniovsky, Kazuya Ishihara, Tetsuya Matsumura, Shin'ichi Takeuchi, Haruyuki Ohkuma, Koji Nishigaki, Hirokazu Suzuki, Masahiro Kazayama, Toyohiko Yoshida, Koji Tsuchihashi
A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications. CICC (1998)
Edgar Holmann, Toyohiko Yoshida, Akira Yamada, Shin-ichi Uramoto
Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding. J. VLSI Signal Process. 18 (2) (1998)
Hisakazu Sato, Edgar Holmann, Toyohiko Yoshida, Masahito Matsuo, Toru Kengaku
A dual-issue RISC processor for multimedia signal processing. ICASSP (1997)
Mamoru Sakamoto, Toyohiko Yoshida, Yasuhiro Nunomura, Yukihiko Shimazu
Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor. ICCD (1996)
Masahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saitoh, Jun-ichi Hinata
A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface. ICCD (1994)
Toyohiko Yoshida, Toru Shimisu, Shigeo Mizugaki, Jun-ichi Hinata
The Gmicro/100 32-bit microprocessor. IEEE Micro 11 (4) (1991)
Toyohiko Yoshida, Masahito Matsuo, Tatsuya Ueda, Yuichi Saito
A strategy for avoiding pipeline interlock delays in a microprocessor. ICCD (1990)
Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito
A 32-bit microprocessor with high performance bit-map manipulation instructions. ICCD (1989)
Tom Shimizu, Toyohiko Yoshida, Yuichi Saitoh, Masahito Matsuo, Tatsuya Enomoto
A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100. COMPCON (1988)