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A 32-bit microprocessor with high performance bit-map manipulation instructions.
Toru Shimizu
Shunichi Iwata
Yuichi Saito
Toyohiko Yoshida
Masahito Matsuo
Junichi Hinata
Kazunori Saito
Published in:
ICCD (1989)
Keyphrases
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instruction set architecture
maximum a posteriori
random number generator
general purpose
cost effective
logical operations
instruction set
bit vector