Kiyoharu Hamaguchi

Publication Activity (10 Years)

Years Active: 1990-2023
Publications (10 Years): 6

Top Topics

Language Independent

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Kiyoharu Hamaguchi
Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage. IPSJ Trans. Syst. LSI Des. Methodol. 16 (2023)
Kiyoharu Hamaguchi
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2019)
Kiyoharu Hamaguchi
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Mami Miyamoto, Kiyoharu Hamaguchi
Extracting hardware assertions including word-level relations over multiple clock cycles. ISQED (2018)
Kiyoharu Hamaguchi
Applying an SMT Solver to Coverage-Driven Design Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Yosuke Kakiuchi, Kiyoharu Hamaguchi
Coverage-Driven Design Verification Using a Diverse SAT Solver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi
Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts. Inf. Media Technol. 6 (4) (2011)
Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi
Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara
Approximate Model Checking Using a Subset of First-order Logic. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
Checker Generation of Assertions with Local Variables for Model Checking. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. ATVA (2008)
Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition. IEICE Trans. Inf. Syst. (3) (2006)
Yosuke Kakiuchi, A. Kitajima, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
Automatic monitor generation from regular expression based specifications for module interface verification. ISCAS (4) (2005)
Kiyoharu Hamaguchi
Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions. IEICE Trans. Inf. Syst. (3) (2004)
Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas. ATVA (2004)
Kiyoharu Hamaguchi
Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions. HLDVT (2001)
Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs. FMCAD (2000)
Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction. COCOON (2000)
Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi
Another Look at LTL Model Checking. Formal Methods Syst. Des. 10 (1) (1997)
Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima
Efficient construction of binary moment diagrams for verifying arithmetic circuits. ICCAD (1995)
Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi
Another Look at LTL Model Checking. CAV (1994)
Seiichiro Tani, Kiyoharu Hamaguchi, Shuzo Yajima
The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams. ISAAC (1993)
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic. CAV (1992)
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
Infinity-Regular Temporal Logic and its Model Checking Problem. Theor. Comput. Sci. 103 (2) (1992)
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic. CAV (1991)
Hiromi Hiraishi, Kiyoharu Hamaguchi, Hiroyuki Ochi, Shuzo Yajima
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. CAV (1991)
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity. CAV (DIMACS/AMS volume) (1990)
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity. CAV (1990)
Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi
Vectorized Model Checking for Computation Tree Logic. CAV (DIMACS/AMS volume) (1990)
Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi
Vectorized Model Checking for Computation Tree Logic. CAV (1990)