Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic.
Kiyoharu HamaguchiHiromi HiraishiShuzo YajimaPublished in: CAV (1992)
Keyphrases
- temporal logic
- model checking
- concurrent systems
- verification method
- formal verification
- satisfiability problem
- functional verification
- model checker
- bounded model checking
- formal specification language
- design methodology
- modal logic
- computation tree logic
- mazurkiewicz traces
- reactive systems
- symbolic model checking
- circuit design
- formal methods
- epistemic logic
- dynamic constraints
- conceptual design
- finite state
- design process
- np complete