Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation.
Takahiro KakimotoHiroyuki OchiTakao TsudaPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2002)
Keyphrases
- low power
- vlsi architecture
- cmos technology
- power consumption
- low cost
- high speed
- single chip
- low power consumption
- ultra low power
- logic circuits
- gate array
- power dissipation
- vlsi implementation
- digital signal processing
- design methodology
- layout design
- mixed signal
- high power
- efficient implementation
- design process
- wireless transmission
- vlsi circuits
- nm technology
- real time
- latent semantic indexing
- hardware and software
- general purpose
- image processing